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dpavlin |
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/* |
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* PearPC |
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* usb.cc |
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* |
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* Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) |
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* |
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* References: |
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* [1] OpenHCI - Open Host Controller Interface Specification for USB |
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* Revision 1.0a - hcir1_0a.pdf |
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* [2] Linux USB ohci-driver |
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
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* (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include "debug/tracers.h" |
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#include "system/arch/sysendian.h" |
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#include "io/pci/pci.h" |
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#include "usb.h" |
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#include <cstring> |
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#define NUM_INTS 32 /* part of the OHCI standard */ |
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#define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */ |
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struct ohci_hcca { |
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uint32 int_table[NUM_INTS]; /* Interrupt ED table */ |
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uint16 frame_no; /* current frame number */ |
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uint16 pad1; /* set to 0 on each frame_no change */ |
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uint32 done_head; /* info returned for an interrupt */ |
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uint8 reserved_for_hc[116]; |
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} PACKED; |
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// [1].122 |
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#define OHCI_REG_REVISION 0x00 // [1].123 |
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#define OHCI_REG_CONTROL 0x04 // [1].123 |
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#define OHCI_REG_CMDSTATUS 0x08 // [1].126 |
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#define OHCI_REG_INTRSTATUS 0x0c // [1].126 |
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#define OHCI_REG_INTRENABLE 0x10 // [1].126 |
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#define OHCI_REG_INTRDISABLE 0x14 // [1].126 |
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#define OHCI_REG_HCCA 0x18 // [1].126 |
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#define OHCI_REG_ED_PERIODCUR 0x1c // [1].126 |
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#define OHCI_REG_ED_CONTROL_HD 0x20 // [1].126 |
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#define OHCI_REG_ED_CONTROL_CUR 0x24 // [1].126 |
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#define OHCI_REG_ED_BULK_HD 0x28 // [1].126 |
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#define OHCI_REG_ED_BULK_CUR 0x2c // [1].126 |
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#define OHCI_REG_DONEHEAD 0x30 // [1].126 |
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#define OHCI_REG_FMINTERVAL 0x34 // [1].126 |
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#define OHCI_REG_FMREMAIN 0x38 // [1].126 |
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#define OHCI_REG_FMNUMBER 0x3c // [1].126 |
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#define OHCI_REG_PERIODICSTART 0x40 // [1].126 |
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#define OHCI_REG_LSTHRESH 0x44 // [1].126 |
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#define OHCI_REG_ROOTHUB_A 0x48 |
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#define OHCI_REG_ROOTHUB_B 0x4c |
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#define OHCI_REG_ROOTHUB_STAT 0x50 |
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#define OHCI_REG_ROOTHUB_PORTS 0x54 |
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/* |
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* bits in ohci_hcregs.control |
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*/ |
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#define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
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#define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
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#define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
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#define OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
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#define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
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#define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
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#define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
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#define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
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#define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
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/* pre-shifted values for HCFS */ |
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# define OHCI_USB_RESET (0 << 6) |
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# define OHCI_USB_RESUME (1 << 6) |
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# define OHCI_USB_OPER (2 << 6) |
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# define OHCI_USB_SUSPEND (3 << 6) |
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/* |
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* bits in ohci_hcregs.{intrstatus|intrenable|intrdisable} |
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*/ |
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#define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
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#define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
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#define OHCI_INTR_SF (1 << 2) /* start frame */ |
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#define OHCI_INTR_RD (1 << 3) /* resume detect */ |
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#define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
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#define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
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#define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
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#define OHCI_INTR_OC (1 << 30) /* ownership change */ |
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#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
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/* |
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* bits in ohci_hcregs.cmdstatus |
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*/ |
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#define OHCI_HCR (1 << 0) /* host controller reset */ |
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#define OHCI_CLF (1 << 1) /* control list filled */ |
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#define OHCI_BLF (1 << 2) /* bulk list filled */ |
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#define OHCI_OCR (1 << 3) /* ownership change request */ |
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#define OHCI_SOC (3 << 16) /* scheduling overrun count */ |
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/* |
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* bits in ohci_hcregs.roothub.portstatus [1].142 |
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*/ |
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#define OHCI_RH_PS_CCS (1 << 0) /* current connect status */ |
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#define OHCI_RH_PS_PES (1 << 1) /* port enable status */ |
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#define OHCI_RH_PS_PSS (1 << 2) /* port suspend status */ |
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#define OHCI_RH_PS_POCI (1 << 3) /* port overrun current indicator */ |
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#define OHCI_RH_PS_PRS (1 << 4) /* port reset status */ |
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#define OHCI_RH_PS_PPS (1 << 8) /* port power status */ |
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#define OHCI_RH_PS_LSDA (1 << 8) /* low speed device attached */ |
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#define OHCI_RH_PS_CSC (1 << 16) /* connect status change */ |
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#define OHCI_RH_PS_PESC (1 << 17) /* port enable status change */ |
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#define OHCI_RH_PS_PSSC (1 << 18) /* port suspend status change */ |
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#define OHCI_RH_PS_OCIC (1 << 19) /* overrun current indicator change */ |
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#define OHCI_RH_PS_PRSC (1 << 20) /* port reset status change */ |
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struct ohci_hcregs { |
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/* control and status registers */ |
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uint32 control; |
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uint32 cmdstatus; |
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uint32 intrstatus; |
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uint32 intrenable; |
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uint32 intrdisable; |
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/* memory pointers */ |
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uint32 hcca; |
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uint32 ed_periodcurrent; |
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uint32 ed_controlhead; |
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uint32 ed_controlcurrent; |
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uint32 ed_bulkhead; |
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uint32 ed_bulkcurrent; |
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uint32 donehead; |
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/* frame counters */ |
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uint32 fminterval; |
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uint32 fmremaining; |
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uint32 fmnumber; |
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uint32 periodicstart; |
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uint32 lsthresh; |
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/* Root hub ports */ |
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struct ohci_roothub_regs { |
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uint32 a; |
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uint32 b; |
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uint32 status; |
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uint32 portstatus[MAX_ROOT_PORTS]; |
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} roothub; |
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}; |
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static inline const char *hc_regname(uint32 a) |
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{ |
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a >>= 2; |
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if (a > 20) return "unknown"; |
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char *names[] = {"revision","control","cmdstatus","intrstatus","intrenable", |
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"intrdisable","hcca","ed_periodcurrent","ed_controlhead","ed_controlcurrent", |
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"ed_bulkhead","ed_bulkcurrent","donehead","fminterval","fmremaining", |
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"fmnumber","periodicstart", "lsthresh", "roothub.a", "roothub.b", "roothub.status"}; |
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return names[a]; |
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} |
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extern bool gSinglestep; |
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/* |
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* |
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*/ |
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class PCI_USB: public PCI_Device { |
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public: |
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ohci_hcregs hcregs; |
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uint rootport_count; |
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PCI_USB() |
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:PCI_Device("pci-usb", 0x01, 0x06) |
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{ |
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mIORegSize[0] = 0x1000; |
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mIORegType[0] = PCI_ADDRESS_SPACE_MEM; |
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mConfig[0x00] = 0x45; // vendor ID |
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mConfig[0x01] = 0x10; |
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mConfig[0x02] = 0x61; // unit ID |
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mConfig[0x03] = 0xc8; |
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mConfig[0x08] = 0x10; // revision |
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mConfig[0x09] = 0x10; // |
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mConfig[0x0a] = 0x03; // |
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mConfig[0x0b] = 0x0c; // |
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mConfig[0x0e] = 0x00; // header-type |
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assignMemAddress(0, 0x80881000); |
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mConfig[0x3c] = 0x03; |
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mConfig[0x3d] = 0x03; |
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mConfig[0x3e] = 0x03; |
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mConfig[0x3f] = 0x03; |
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rootport_count = 1; |
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reset(); |
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} |
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void reset() |
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{ |
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memset(&hcregs, 0, sizeof hcregs); |
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hcregs.fminterval = 0x2edf; // [1].134 |
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hcregs.lsthresh = 0x628; // [1].137 |
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hcregs.roothub.a = 0 // [1].138 |
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| (1<<12) // No overcurrent protection supported |
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| (0<<10) // always 0 |
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| (1<<9) // Ports are always powered on when the HC is powered on |
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| (0<<8) // all ports are powered at the same time. |
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| rootport_count; // number of rootports |
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// hcregs.roothub.portstatus[0] = ; |
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} |
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virtual bool readDeviceMem(uint r, uint32 address, uint32 &data, uint size) |
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{ |
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if (r != 0) return false; |
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if (size != 4) return false; |
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IO_USB_TRACE("read(r=%d, a=%08x (%s), %d)\n", r, address, hc_regname(address), size); |
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switch (address) { |
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case OHCI_REG_REVISION: |
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// [1].123 |
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data = 0x10; |
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break; |
| 232 |
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case OHCI_REG_CONTROL: |
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data = hcregs.control; |
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break; |
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case OHCI_REG_CMDSTATUS: |
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data = hcregs.cmdstatus; |
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break; |
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case OHCI_REG_INTRSTATUS: |
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data = hcregs.intrstatus; |
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break; |
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case OHCI_REG_INTRENABLE: |
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data = hcregs.intrenable; |
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break; |
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case OHCI_REG_INTRDISABLE: |
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data = hcregs.intrdisable; |
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break; |
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case OHCI_REG_HCCA: |
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data = hcregs.hcca; |
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break; |
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case OHCI_REG_ED_PERIODCUR: |
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data = hcregs.ed_periodcurrent; |
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break; |
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case OHCI_REG_ED_CONTROL_HD: |
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data = hcregs.ed_controlhead; |
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break; |
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case OHCI_REG_ED_CONTROL_CUR: |
| 257 |
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data = hcregs.ed_controlcurrent; |
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break; |
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case OHCI_REG_ED_BULK_HD: |
| 260 |
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data = hcregs.ed_bulkhead; |
| 261 |
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break; |
| 262 |
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case OHCI_REG_ED_BULK_CUR: |
| 263 |
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data = hcregs.ed_bulkcurrent; |
| 264 |
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break; |
| 265 |
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case OHCI_REG_DONEHEAD: |
| 266 |
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data = hcregs.donehead; |
| 267 |
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break; |
| 268 |
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case OHCI_REG_FMINTERVAL: |
| 269 |
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data = hcregs.fminterval; |
| 270 |
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break; |
| 271 |
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case OHCI_REG_FMREMAIN: |
| 272 |
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data = hcregs.fmremaining; |
| 273 |
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break; |
| 274 |
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case OHCI_REG_FMNUMBER: |
| 275 |
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data = hcregs.fmnumber; |
| 276 |
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break; |
| 277 |
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case OHCI_REG_PERIODICSTART: |
| 278 |
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data = hcregs.periodicstart; |
| 279 |
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break; |
| 280 |
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case OHCI_REG_LSTHRESH: |
| 281 |
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data = hcregs.lsthresh; |
| 282 |
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break; |
| 283 |
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case OHCI_REG_ROOTHUB_A: |
| 284 |
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data = hcregs.roothub.a; |
| 285 |
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break; |
| 286 |
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case OHCI_REG_ROOTHUB_B: |
| 287 |
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data = hcregs.roothub.b; |
| 288 |
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break; |
| 289 |
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case OHCI_REG_ROOTHUB_STAT: |
| 290 |
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data = hcregs.roothub.status; |
| 291 |
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break; |
| 292 |
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default: |
| 293 |
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address -= OHCI_REG_ROOTHUB_PORTS; |
| 294 |
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address >>= 2; |
| 295 |
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if (address < rootport_count) { |
| 296 |
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data = hcregs.roothub.portstatus[address]; |
| 297 |
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break; |
| 298 |
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} |
| 299 |
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return false; |
| 300 |
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} |
| 301 |
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| 302 |
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// gSinglestep = true; |
| 303 |
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return true; |
| 304 |
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} |
| 305 |
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| 306 |
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virtual bool writeDeviceMem(uint r, uint32 address, uint32 data, uint size) |
| 307 |
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{ |
| 308 |
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if (r != 0) return false; |
| 309 |
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if (size != 4) return false; |
| 310 |
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IO_USB_TRACE("write(r=%d, a=%08x (%s), data=%08x, %d)\n", r, address, hc_regname(address), data, size); |
| 311 |
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| 312 |
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switch (address) { |
| 313 |
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case OHCI_REG_REVISION: |
| 314 |
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// [1].123 |
| 315 |
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IO_USB_WARN("revision is read only.\n"); |
| 316 |
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return true; |
| 317 |
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case OHCI_REG_CONTROL: |
| 318 |
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hcregs.control = data; |
| 319 |
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break; |
| 320 |
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case OHCI_REG_CMDSTATUS: |
| 321 |
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if (data & OHCI_HCR) { |
| 322 |
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reset(); |
| 323 |
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return true; |
| 324 |
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} |
| 325 |
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hcregs.cmdstatus = data; |
| 326 |
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break; |
| 327 |
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case OHCI_REG_INTRSTATUS: |
| 328 |
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hcregs.intrstatus = data; |
| 329 |
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break; |
| 330 |
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case OHCI_REG_INTRENABLE: |
| 331 |
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hcregs.intrenable = data; |
| 332 |
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break; |
| 333 |
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case OHCI_REG_INTRDISABLE: |
| 334 |
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hcregs.intrdisable = data; |
| 335 |
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break; |
| 336 |
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case OHCI_REG_HCCA: |
| 337 |
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hcregs.hcca = data; |
| 338 |
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break; |
| 339 |
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case OHCI_REG_ED_PERIODCUR: |
| 340 |
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hcregs.ed_periodcurrent = data; |
| 341 |
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break; |
| 342 |
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case OHCI_REG_ED_CONTROL_HD: |
| 343 |
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hcregs.ed_controlhead = data; |
| 344 |
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break; |
| 345 |
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|
case OHCI_REG_ED_CONTROL_CUR: |
| 346 |
|
|
hcregs.ed_controlcurrent = data; |
| 347 |
|
|
break; |
| 348 |
|
|
case OHCI_REG_ED_BULK_HD: |
| 349 |
|
|
hcregs.ed_bulkhead = data; |
| 350 |
|
|
break; |
| 351 |
|
|
case OHCI_REG_ED_BULK_CUR: |
| 352 |
|
|
hcregs.ed_bulkcurrent = data; |
| 353 |
|
|
break; |
| 354 |
|
|
case OHCI_REG_DONEHEAD: |
| 355 |
|
|
hcregs.donehead = data; |
| 356 |
|
|
break; |
| 357 |
|
|
case OHCI_REG_FMINTERVAL: |
| 358 |
|
|
hcregs.fminterval = data; |
| 359 |
|
|
break; |
| 360 |
|
|
case OHCI_REG_FMREMAIN: |
| 361 |
|
|
hcregs.fmremaining = data; |
| 362 |
|
|
break; |
| 363 |
|
|
case OHCI_REG_FMNUMBER: |
| 364 |
|
|
hcregs.fmnumber = data; |
| 365 |
|
|
break; |
| 366 |
|
|
case OHCI_REG_PERIODICSTART: |
| 367 |
|
|
hcregs.periodicstart = data; |
| 368 |
|
|
break; |
| 369 |
|
|
case OHCI_REG_LSTHRESH: |
| 370 |
|
|
hcregs.lsthresh = data; |
| 371 |
|
|
break; |
| 372 |
|
|
case OHCI_REG_ROOTHUB_A: |
| 373 |
|
|
hcregs.roothub.a = data; |
| 374 |
|
|
break; |
| 375 |
|
|
case OHCI_REG_ROOTHUB_B: |
| 376 |
|
|
hcregs.roothub.b = data; |
| 377 |
|
|
break; |
| 378 |
|
|
case OHCI_REG_ROOTHUB_STAT: |
| 379 |
|
|
hcregs.roothub.status = data; |
| 380 |
|
|
break; |
| 381 |
|
|
default: |
| 382 |
|
|
address -= OHCI_REG_ROOTHUB_PORTS; |
| 383 |
|
|
address >>= 2; |
| 384 |
|
|
if (address < rootport_count) { |
| 385 |
|
|
if (data & OHCI_RH_PS_CCS) { |
| 386 |
|
|
// writing 1 to CCS clears PES |
| 387 |
|
|
hcregs.roothub.portstatus[address] &= ~OHCI_RH_PS_PES; |
| 388 |
|
|
} |
| 389 |
|
|
|
| 390 |
|
|
// writing 1 to these bits clears them |
| 391 |
|
|
hcregs.roothub.portstatus[address] &= ~(data & |
| 392 |
|
|
(OHCI_RH_PS_CSC | OHCI_RH_PS_PESC | OHCI_RH_PS_PSSC |
| 393 |
|
|
| OHCI_RH_PS_OCIC | OHCI_RH_PS_PRSC)); |
| 394 |
|
|
|
| 395 |
|
|
// writing 1 to these bits set them only if CCS is set |
| 396 |
|
|
uint32 p = data & OHCI_RH_PS_PES | OHCI_RH_PS_PSS | OHCI_RH_PS_PRS; |
| 397 |
|
|
if (p) { |
| 398 |
|
|
if (hcregs.roothub.portstatus[address] & OHCI_RH_PS_CCS) { |
| 399 |
|
|
hcregs.roothub.portstatus[address] |= p; |
| 400 |
|
|
} else { |
| 401 |
|
|
// attempt to enable/suspend/reset disconnected port |
| 402 |
|
|
hcregs.roothub.portstatus[address] |= OHCI_RH_PS_CSC; |
| 403 |
|
|
} |
| 404 |
|
|
} |
| 405 |
|
|
|
| 406 |
|
|
// we dont support power switching |
| 407 |
|
|
hcregs.roothub.portstatus[address] |= OHCI_RH_PS_PPS; |
| 408 |
|
|
break; |
| 409 |
|
|
} |
| 410 |
|
|
} |
| 411 |
|
|
|
| 412 |
|
|
// gSinglestep = true; |
| 413 |
|
|
return true; |
| 414 |
|
|
} |
| 415 |
|
|
|
| 416 |
|
|
}; |
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
#include "configparser.h" |
| 420 |
|
|
|
| 421 |
|
|
#define USB_KEY_INSTALLED "pci_usb_installed" |
| 422 |
|
|
|
| 423 |
|
|
void usb_init() |
| 424 |
|
|
{ |
| 425 |
|
|
if (gConfig->getConfigInt(USB_KEY_INSTALLED)) { |
| 426 |
|
|
gPCI_Devices->insert(new PCI_USB()); |
| 427 |
|
|
} |
| 428 |
|
|
} |
| 429 |
|
|
|
| 430 |
|
|
void usb_done() |
| 431 |
|
|
{ |
| 432 |
|
|
} |
| 433 |
|
|
|
| 434 |
|
|
void usb_init_config() |
| 435 |
|
|
{ |
| 436 |
|
|
gConfig->acceptConfigEntryIntDef(USB_KEY_INSTALLED, 0); |
| 437 |
|
|
} |
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