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/* |
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* PearPC |
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* pci.cc |
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* |
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* Copyright (C) 2003 Sebastian Biallas (sb@biallas.net) |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#include "debug/tracers.h" |
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#include "macio.h" |
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|
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#define MACIO_DBDMA_ADDRESS_CONTROL 0x00 |
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#define MACIO_DBDMA_ADDRESS_STATUS 0x04 |
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#define MACIO_DBDMA_ADDRESS_CMD_PTR_HI 0x08 |
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#define MACIO_DBDMA_ADDRESS_CMD_PTR_LO 0x0c |
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#define MACIO_DBDMA_ADDRESS_INTR_SEL 0x10 |
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#define MACIO_DBDMA_ADDRESS_BRANCH_SEL 0x14 |
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#define MACIO_DBDMA_ADDRESS_WAIT_SEL 0x18 |
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#define MACIO_DBDMA_ADDRESS_MODES 0x1c |
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#define MACIO_DBDMA_ADDRESS_DATA_PTR_HI 0x20 |
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#define MACIO_DBDMA_ADDRESS_DATA_PTR_LO 0x24 |
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#define MACIO_DBDMA_ADDRESS_ADDRESS_HI 0x2c |
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|
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/* |
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* Channel control and status flags |
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*/ |
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#define MACIO_DBDMA_RUN 0x8000 |
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#define MACIO_DBDMA_PAUSE 0x4000 |
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#define MACIO_DBDMA_FLUSH 0x2000 |
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#define MACIO_DBDMA_WAKE 0x1000 |
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#define MACIO_DBDMA_DEAD 0x800 |
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#define MACIO_DBDMA_ACTIVE 0x400 |
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#define MACIO_DBDMA_BT 0x100 |
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#define MACIO_DBDMA_S7 0x80 |
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#define MACIO_DBDMA_S6 0x40 |
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#define MACIO_DBDMA_S5 0x20 |
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#define MACIO_DBDMA_S4 0x10 |
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#define MACIO_DBDMA_S3 0x8 |
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#define MACIO_DBDMA_S2 0x4 |
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#define MACIO_DBDMA_S1 0x2 |
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#define MACIO_DBDMA_S0 0x1 |
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|
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/* |
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* commands |
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*/ |
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|
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#define MACIO_DBDMA_CMD_OUTPUT_MORE 0 |
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#define MACIO_DBDMA_CMD_OUTPUT_LAST 1 |
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#define MACIO_DBDMA_CMD_INPUT_MORE 2 |
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#define MACIO_DBDMA_CMD_INPUT_LAST 3 |
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#define MACIO_DBDMA_CMD_STORE_QUAD 4 |
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#define MACIO_DBDMA_CMD_LOAD_QUAD 5 |
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#define MACIO_DBDMA_CMD_NOP 6 |
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#define MACIO_DBDMA_CMD_STOP 7 |
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|
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/* |
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* keys |
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*/ |
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|
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#define MACIO_DBDMA_KEY_STREAM0 0 |
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#define MACIO_DBDMA_KEY_STREAM1 1 |
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#define MACIO_DBDMA_KEY_STREAM2 2 |
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#define MACIO_DBDMA_KEY_STREAM3 3 |
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#define MACIO_DBDMA_KEY_REGS 5 |
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#define MACIO_DBDMA_KEY_SYSTEM 6 |
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#define MACIO_DBDMA_KEY_DEVICE 7 |
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|
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#define MACIO_DBDMA_INT_NEVER 0 |
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#define MACIO_DBDMA_INT_IF_TRUE 1 |
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#define MACIO_DBDMA_INT_IF_FALSE 2 |
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#define MACIO_DBDMA_INT_ALWAYS 3 |
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|
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#define MACIO_DBDMA_BRANCH_NEVER 0 |
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#define MACIO_DBDMA_BRANCH_IF_TRUE 1 |
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#define MACIO_DBDMA_BRANCH_IF_FALSE 2 |
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#define MACIO_DBDMA_BRANCH_ALWAYS 3 |
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|
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#define MACIO_DBDMA_WAIT_NEVER 0 |
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#define MACIO_DBDMA_WAIT_IF_TRUE 1 |
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#define MACIO_DBDMA_WAIT_IF_FALSE 2 |
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#define MACIO_DBDMA_WAIT_ALWAYS 3 |
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|
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struct MacIO_DBDMA_ChannelRegs { |
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uint32 control; |
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uint32 status; |
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uint32 commandPtrHi; |
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uint32 commandPtrLo; |
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uint32 interruptSelect; |
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uint32 branchSelect; |
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uint32 waitSelect; |
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uint32 transferModes; |
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uint32 data2PtrHi; |
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uint32 data2PtrLo; |
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uint32 addressHi; |
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}; |
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|
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PCI_MacIO::PCI_MacIO() |
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:PCI_Device("pci-macio", 0x01, 0x05) |
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{ |
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mIORegSize[0] = 0x80000; |
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mIORegType[0] = PCI_ADDRESS_SPACE_MEM; |
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|
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mConfig[0x00] = 0x6b; // vendor ID |
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mConfig[0x01] = 0x10; |
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mConfig[0x02] = 0x17; // unit ID |
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mConfig[0x03] = 0x00; |
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|
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mConfig[0x08] = 0x00; // revision |
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mConfig[0x09] = 0x00; // programming interface code |
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mConfig[0x0a] = 0x00; // pci2pci |
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mConfig[0x0b] = 0xff; // bridge |
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|
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mConfig[0x0e] = 0x00; // header-type |
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|
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assignMemAddress(0, 0x80800000); |
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|
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mConfig[0x3c] = 0x18; |
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mConfig[0x3d] = 1; |
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mConfig[0x3e] = 0; |
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mConfig[0x3f] = 0; |
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} |
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|
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bool PCI_MacIO::readDeviceMem(uint r, uint32 address, uint32 &data, uint size) |
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{ |
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if (r==0 && address >= 0x8000 && address < 0x8100) { |
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address -= 0x8000; |
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IO_MACIO_TRACE("dbdma: read(%d) @%08x\n", size, address); |
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if (size != 4) IO_MACIO_ERR("read with size != 4\n"); |
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data = 0; |
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switch (address) { |
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case MACIO_DBDMA_ADDRESS_CONTROL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_STATUS: |
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return true; |
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case MACIO_DBDMA_ADDRESS_CMD_PTR_HI: |
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return true; |
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case MACIO_DBDMA_ADDRESS_CMD_PTR_LO: |
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return true; |
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case MACIO_DBDMA_ADDRESS_INTR_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_BRANCH_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_WAIT_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_MODES: |
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return true; |
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case MACIO_DBDMA_ADDRESS_DATA_PTR_HI: |
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return true; |
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case MACIO_DBDMA_ADDRESS_DATA_PTR_LO: |
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return true; |
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case MACIO_DBDMA_ADDRESS_ADDRESS_HI: |
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return true; |
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} |
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} |
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return false; |
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} |
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|
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bool PCI_MacIO::writeDeviceMem(uint r, uint32 address, uint32 data, uint size) |
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{ |
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if (r==0 && address >= 0x8000 && address < 0x8100) { |
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address -= 0x8000; |
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IO_MACIO_TRACE("dbdma: write(%d) @%08x: %08x\n", size, address, data); |
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if (size != 4) IO_MACIO_ERR("read with size != 4\n"); |
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switch (address) { |
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case MACIO_DBDMA_ADDRESS_CONTROL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_STATUS: |
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return true; |
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case MACIO_DBDMA_ADDRESS_CMD_PTR_HI: |
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return true; |
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case MACIO_DBDMA_ADDRESS_CMD_PTR_LO: |
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return true; |
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case MACIO_DBDMA_ADDRESS_INTR_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_BRANCH_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_WAIT_SEL: |
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return true; |
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case MACIO_DBDMA_ADDRESS_MODES: |
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return true; |
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case MACIO_DBDMA_ADDRESS_DATA_PTR_HI: |
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return true; |
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case MACIO_DBDMA_ADDRESS_DATA_PTR_LO: |
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return true; |
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case MACIO_DBDMA_ADDRESS_ADDRESS_HI: |
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return true; |
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} |
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} |
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return false; |
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} |
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|
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void macio_init() |
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{ |
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gPCI_Devices->insert(new PCI_MacIO()); |
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} |
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|
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void macio_done() |
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{ |
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} |
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|
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void macio_init_config() |
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{ |
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} |