src/debug/ppcopc.h

/*
 *      HT Editor
 *      ppcopc.cc
 *
 *      Copyright (C) 1999-2003 Sebastian Biallas (sb@biallas.net)
 *      Copyright 1994, 1995, 1999, 2000, 2001, 2002
 *      Free Software Foundation, Inc.
 *      Written by Ian Lance Taylor, Cygnus Support 
 *
 *      This program is free software; you can redistribute it and/or modify
 *      it under the terms of the GNU General Public License version 2 as
 *      published by the Free Software Foundation.
 *
 *      This program is distributed in the hope that it will be useful,
 *      but WITHOUT ANY WARRANTY; without even the implied warranty of
 *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *      GNU General Public License for more details.
 *
 *      You should have received a copy of the GNU General Public License
 *      along with this program; if not, write to the Free Software
 *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef __PPC_OPC_H__
#define __PPC_OPC_H__

#include "system/types.h"

/* The opcode table is an array of struct powerpc_opcode.  */
struct powerpc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
        operands are zeroes.  */
  uint32 opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
        mask containing ones indicating those bits which must match the
        opcode field, and zeroes indicating those bits which need not
        match (and are presumably filled in by operands).  */
  uint32 mask;

  /* One bit flags for the opcode.  These are used to indicate which
        specific processors support the instructions.  The defined values
        are listed below.  */
  uint32 flags;

  /* An array of operand codes.  Each code is an index into the
        operand table.  They appear in the order which the operands must
        appear in assembly code, and are terminated by a zero.  */
  byte operands[8];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;

/* Values defined for the flags field of a struct powerpc_opcode.  */

/* Opcode is defined for the PowerPC architecture.  */
#define PPC_OPCODE_PPC (01)

/* Opcode is defined for the POWER (RS/6000) architecture.  */
#define PPC_OPCODE_POWER (02)

/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
#define PPC_OPCODE_POWER2 (04)

/* Opcode is only defined on 32 bit architectures.  */
#define PPC_OPCODE_32 (010)

/* Opcode is only defined on 64 bit architectures.  */
#define PPC_OPCODE_64 (020)

/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
   but it also supports many additional POWER instructions.  */
#define PPC_OPCODE_601 (040)

/* Opcode is supported in both the Power and PowerPC architectures
   (ie, compiler's -mcpu=common or assembler's -mcom).  */
#define PPC_OPCODE_COMMON (0100)

/* Opcode is supported for any Power or PowerPC platform (this is
   for the assembler's -many option, and it eliminates duplicates).  */
#define PPC_OPCODE_ANY (0200)

/* Opcode is supported as part of the 64-bit bridge.  */
#define PPC_OPCODE_64_BRIDGE (0400)

/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC (01000)

/* Opcode is supported by PowerPC 403 processor.  */
#define PPC_OPCODE_403 (02000)

/* Opcode is supported by PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE (04000)

/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE64 (010000)

/* Opcode is only supported by Power4 architecture.  */
#define PPC_OPCODE_POWER4 (020000)

/* Opcode isn't supported by Power4 architecture.  */
#define PPC_OPCODE_NOPOWER4 (040000)

/* Opcode is only supported by POWERPC Classic architecture.  */
#define PPC_OPCODE_CLASSIC (0100000)

/* Opcode is only supported by e500x2 Core.  */
#define PPC_OPCODE_SPE     (0200000)

/* Opcode is supported by e500x2 Integer select APU.  */
#define PPC_OPCODE_ISEL     (0400000)

/* Opcode is an e500 SPE floating point instruction.  */
#define PPC_OPCODE_EFS      (01000000)

/* Opcode is supported by branch locking APU.  */
#define PPC_OPCODE_BRLOCK   (02000000)

/* Opcode is supported by performance monitor APU.  */
#define PPC_OPCODE_PMR      (04000000)

/* Opcode is supported by cache locking APU.  */
#define PPC_OPCODE_CACHELCK (010000000)

/* Opcode is supported by machine check APU.  */
#define PPC_OPCODE_RFMCI    (020000000)

/* A macro to extract the major opcode from an instruction.  */
#define PPC_OP(i) (((i) >> 26) & 0x3f)

/* The operands table is an array of struct powerpc_operand.  */

struct powerpc_operand
{
  /* The number of bits in the operand.  */
  byte bits;

  /* How far the operand is left shifted in the instruction.  */
  byte shift;

  /* Extraction function.  This is used by the disassembler.  To
        extract this operand type from an instruction, check this field.

        If it is NULL, compute
            op = ((i) >> o->shift) & ((1 << o->bits) - 1);
         if ((o->flags & PPC_OPERAND_SIGNED) != 0
                && (op & (1 << (o->bits - 1))) != 0)
           op -= 1 << o->bits;
        (i is the instruction, o is a pointer to this structure, and op
        is the result; this assumes twos complement arithmetic).

        If this field is not NULL, then simply call it with the
        instruction value.  It will return the value of the operand.  If
        the INVALID argument is not NULL, *INVALID will be set to
        non-zero if this operand type can not actually be extracted from
        this operand (i.e., the instruction does not match).  If the
        operand is valid, *INVALID will not be changed.  */
  uint32 (*extract)(uint32 instruction, bool *invalid);

  /* One bit syntax flags.  */
  uint32 flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the powerpc_opcodes table.  */

extern const struct powerpc_operand powerpc_operands[];

/* Values defined for the flags field of a struct powerpc_operand.  */

/* This operand takes signed values.  */
#define PPC_OPERAND_SIGNED (01)

/* This operand takes signed values, but also accepts a full positive
   range of values when running in 32 bit mode.  That is, if bits is
   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
   this flag is ignored.  */
#define PPC_OPERAND_SIGNOPT (02)

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics such as mr, for which two
   operands fields are identical.  The assembler should call the
   insert function with any op value.  The disassembler should call
   the extract function, ignore the return value, and check the value
   placed in the valid argument.  */
#define PPC_OPERAND_FAKE (04)

/* The next operand should be wrapped in parentheses rather than
   separated from this one by a comma.  This is used for the load and
   store instructions which want their operands to look like
          reg,displacement(reg)
   */
#define PPC_OPERAND_PARENS (010)

/* This operand may use the symbolic names for the CR fields, which
   are
          lt  0 gt  1   eq  2   so  3   un  3
          cr0 0 cr1 1   cr2 2   cr3 3
          cr4 4 cr5 5   cr6 6   cr7 7
   These may be combined arithmetically, as in cr2*4+gt.  These are
   only supported on the PowerPC, not the POWER.  */
#define PPC_OPERAND_CR (020)

/* This operand names a register.  The disassembler uses this to print
   register names with a leading 'r'.  */
#define PPC_OPERAND_GPR (040)

/* This operand names a floating point register.  The disassembler
   prints these with a leading 'f'.  */
#define PPC_OPERAND_FPR (0100)

/* This operand is a relative branch displacement.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_RELATIVE (0200)

/* This operand is an absolute branch address.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_ABSOLUTE (0400)

/* This operand is optional, and is zero if omitted.  This is used for
   the optional BF and L fields in the comparison instructions.  The
   assembler must count the number of operands remaining on the line,
   and the number of operands remaining for the opcode, and decide
   whether this operand is present or not.  The disassembler should
   print this operand out only if it is not zero.  */
#define PPC_OPERAND_OPTIONAL (01000)

/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
   is omitted, then for the next operand use this operand value plus
   1, ignoring the next operand field for the opcode.  This wretched
   hack is needed because the Power rotate instructions can take
   either 4 or 5 operands.  The disassembler should print this operand
   out regardless of the PPC_OPERAND_OPTIONAL field.  */
#define PPC_OPERAND_NEXT (02000)

/* This operand should be regarded as a negative number for the
   purposes of overflow checking (i.e., the normal most negative
   number is disallowed and one more than the normal most positive
   number is allowed).  This flag will only be set for a signed
   operand.  */
#define PPC_OPERAND_NEGATIVE (04000)

/* This operand names a vector unit register.  The disassembler
   prints these with a leading 'v'.  */
#define PPC_OPERAND_VR (010000)

/* This operand is for the DS field in a DS form instruction.  */
#define PPC_OPERAND_DS (020000)

#endif
1	dpavlin	1	/*
2			* HT Editor
3			* ppcopc.cc
4			*
5			* Copyright (C) 1999-2003 Sebastian Biallas (sb@biallas.net)
6			* Copyright 1994, 1995, 1999, 2000, 2001, 2002
7			* Free Software Foundation, Inc.
8			* Written by Ian Lance Taylor, Cygnus Support
9			*
10			* This program is free software; you can redistribute it and/or modify
11			* it under the terms of the GNU General Public License version 2 as
12			* published by the Free Software Foundation.
13			*
14			* This program is distributed in the hope that it will be useful,
15			* but WITHOUT ANY WARRANTY; without even the implied warranty of
16			* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17			* GNU General Public License for more details.
18			*
19			* You should have received a copy of the GNU General Public License
20			* along with this program; if not, write to the Free Software
21			* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22			*/
23
24			#ifndef __PPC_OPC_H__
25			#define __PPC_OPC_H__
26
27			#include "system/types.h"
28
29			/* The opcode table is an array of struct powerpc_opcode. */
30			struct powerpc_opcode
31			{
32			/* The opcode name. */
33			const char *name;
34
35			/* The opcode itself. Those bits which will be filled in with
36			operands are zeroes. */
37			uint32 opcode;
38
39			/* The opcode mask. This is used by the disassembler. This is a
40			mask containing ones indicating those bits which must match the
41			opcode field, and zeroes indicating those bits which need not
42			match (and are presumably filled in by operands). */
43			uint32 mask;
44
45			/* One bit flags for the opcode. These are used to indicate which
46			specific processors support the instructions. The defined values
47			are listed below. */
48			uint32 flags;
49
50			/* An array of operand codes. Each code is an index into the
51			operand table. They appear in the order which the operands must
52			appear in assembly code, and are terminated by a zero. */
53			byte operands[8];
54			};
55
56			/* The table itself is sorted by major opcode number, and is otherwise
57			in the order in which the disassembler should consider
58			instructions. */
59			extern const struct powerpc_opcode powerpc_opcodes[];
60			extern const int powerpc_num_opcodes;
61
62			/* Values defined for the flags field of a struct powerpc_opcode. */
63
64			/* Opcode is defined for the PowerPC architecture. */
65			#define PPC_OPCODE_PPC (01)
66
67			/* Opcode is defined for the POWER (RS/6000) architecture. */
68			#define PPC_OPCODE_POWER (02)
69
70			/* Opcode is defined for the POWER2 (Rios 2) architecture. */
71			#define PPC_OPCODE_POWER2 (04)
72
73			/* Opcode is only defined on 32 bit architectures. */
74			#define PPC_OPCODE_32 (010)
75
76			/* Opcode is only defined on 64 bit architectures. */
77			#define PPC_OPCODE_64 (020)
78
79			/* Opcode is supported by the Motorola PowerPC 601 processor. The 601
80			is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
81			but it also supports many additional POWER instructions. */
82			#define PPC_OPCODE_601 (040)
83
84			/* Opcode is supported in both the Power and PowerPC architectures
85			(ie, compiler's -mcpu=common or assembler's -mcom). */
86			#define PPC_OPCODE_COMMON (0100)
87
88			/* Opcode is supported for any Power or PowerPC platform (this is
89			for the assembler's -many option, and it eliminates duplicates). */
90			#define PPC_OPCODE_ANY (0200)
91
92			/* Opcode is supported as part of the 64-bit bridge. */
93			#define PPC_OPCODE_64_BRIDGE (0400)
94
95			/* Opcode is supported by Altivec Vector Unit */
96			#define PPC_OPCODE_ALTIVEC (01000)
97
98			/* Opcode is supported by PowerPC 403 processor. */
99			#define PPC_OPCODE_403 (02000)
100
101			/* Opcode is supported by PowerPC BookE processor. */
102			#define PPC_OPCODE_BOOKE (04000)
103
104			/* Opcode is only supported by 64-bit PowerPC BookE processor. */
105			#define PPC_OPCODE_BOOKE64 (010000)
106
107			/* Opcode is only supported by Power4 architecture. */
108			#define PPC_OPCODE_POWER4 (020000)
109
110			/* Opcode isn't supported by Power4 architecture. */
111			#define PPC_OPCODE_NOPOWER4 (040000)
112
113			/* Opcode is only supported by POWERPC Classic architecture. */
114			#define PPC_OPCODE_CLASSIC (0100000)
115
116			/* Opcode is only supported by e500x2 Core. */
117			#define PPC_OPCODE_SPE (0200000)
118
119			/* Opcode is supported by e500x2 Integer select APU. */
120			#define PPC_OPCODE_ISEL (0400000)
121
122			/* Opcode is an e500 SPE floating point instruction. */
123			#define PPC_OPCODE_EFS (01000000)
124
125			/* Opcode is supported by branch locking APU. */
126			#define PPC_OPCODE_BRLOCK (02000000)
127
128			/* Opcode is supported by performance monitor APU. */
129			#define PPC_OPCODE_PMR (04000000)
130
131			/* Opcode is supported by cache locking APU. */
132			#define PPC_OPCODE_CACHELCK (010000000)
133
134			/* Opcode is supported by machine check APU. */
135			#define PPC_OPCODE_RFMCI (020000000)
136
137			/* A macro to extract the major opcode from an instruction. */
138			#define PPC_OP(i) (((i) >> 26) & 0x3f)
139
140			/* The operands table is an array of struct powerpc_operand. */
141
142			struct powerpc_operand
143			{
144			/* The number of bits in the operand. */
145			byte bits;
146
147			/* How far the operand is left shifted in the instruction. */
148			byte shift;
149
150			/* Extraction function. This is used by the disassembler. To
151			extract this operand type from an instruction, check this field.
152
153			If it is NULL, compute
154			op = ((i) >> o->shift) & ((1 << o->bits) - 1);
155			if ((o->flags & PPC_OPERAND_SIGNED) != 0
156			&& (op & (1 << (o->bits - 1))) != 0)
157			op -= 1 << o->bits;
158			(i is the instruction, o is a pointer to this structure, and op
159			is the result; this assumes twos complement arithmetic).
160
161			If this field is not NULL, then simply call it with the
162			instruction value. It will return the value of the operand. If
163			the INVALID argument is not NULL, *INVALID will be set to
164			non-zero if this operand type can not actually be extracted from
165			this operand (i.e., the instruction does not match). If the
166			operand is valid, INVALID will not be changed. /
167			uint32 (extract)(uint32 instruction, bool invalid);
168
169			/* One bit syntax flags. */
170			uint32 flags;
171			};
172
173			/* Elements in the table are retrieved by indexing with values from
174			the operands field of the powerpc_opcodes table. */
175
176			extern const struct powerpc_operand powerpc_operands[];
177
178			/* Values defined for the flags field of a struct powerpc_operand. */
179
180			/* This operand takes signed values. */
181			#define PPC_OPERAND_SIGNED (01)
182
183			/* This operand takes signed values, but also accepts a full positive
184			range of values when running in 32 bit mode. That is, if bits is
185			16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
186			this flag is ignored. */
187			#define PPC_OPERAND_SIGNOPT (02)
188
189			/* This operand does not actually exist in the assembler input. This
190			is used to support extended mnemonics such as mr, for which two
191			operands fields are identical. The assembler should call the
192			insert function with any op value. The disassembler should call
193			the extract function, ignore the return value, and check the value
194			placed in the valid argument. */
195			#define PPC_OPERAND_FAKE (04)
196
197			/* The next operand should be wrapped in parentheses rather than
198			separated from this one by a comma. This is used for the load and
199			store instructions which want their operands to look like
200			reg,displacement(reg)
201			*/
202			#define PPC_OPERAND_PARENS (010)
203
204			/* This operand may use the symbolic names for the CR fields, which
205			are
206			lt 0 gt 1 eq 2 so 3 un 3
207			cr0 0 cr1 1 cr2 2 cr3 3
208			cr4 4 cr5 5 cr6 6 cr7 7
209			These may be combined arithmetically, as in cr2*4+gt. These are
210			only supported on the PowerPC, not the POWER. */
211			#define PPC_OPERAND_CR (020)
212
213			/* This operand names a register. The disassembler uses this to print
214			register names with a leading 'r'. */
215			#define PPC_OPERAND_GPR (040)
216
217			/* This operand names a floating point register. The disassembler
218			prints these with a leading 'f'. */
219			#define PPC_OPERAND_FPR (0100)
220
221			/* This operand is a relative branch displacement. The disassembler
222			prints these symbolically if possible. */
223			#define PPC_OPERAND_RELATIVE (0200)
224
225			/* This operand is an absolute branch address. The disassembler
226			prints these symbolically if possible. */
227			#define PPC_OPERAND_ABSOLUTE (0400)
228
229			/* This operand is optional, and is zero if omitted. This is used for
230			the optional BF and L fields in the comparison instructions. The
231			assembler must count the number of operands remaining on the line,
232			and the number of operands remaining for the opcode, and decide
233			whether this operand is present or not. The disassembler should
234			print this operand out only if it is not zero. */
235			#define PPC_OPERAND_OPTIONAL (01000)
236
237			/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
238			is omitted, then for the next operand use this operand value plus
239			1, ignoring the next operand field for the opcode. This wretched
240			hack is needed because the Power rotate instructions can take
241			either 4 or 5 operands. The disassembler should print this operand
242			out regardless of the PPC_OPERAND_OPTIONAL field. */
243			#define PPC_OPERAND_NEXT (02000)
244
245			/* This operand should be regarded as a negative number for the
246			purposes of overflow checking (i.e., the normal most negative
247			number is disallowed and one more than the normal most positive
248			number is allowed). This flag will only be set for a signed
249			operand. */
250			#define PPC_OPERAND_NEGATIVE (04000)
251
252			/* This operand names a vector unit register. The disassembler
253			prints these with a leading 'v'. */
254			#define PPC_OPERAND_VR (010000)
255
256			/* This operand is for the DS field in a DS form instruction. */
257			#define PPC_OPERAND_DS (020000)
258
259			#endif