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dpavlin |
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/* |
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* PearPC |
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* common.h |
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* |
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* Copyright (C) 2003-2006 Sebastian Biallas (sb@biallas.net) |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#ifndef __CPU_COMMON_H__ |
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#define __CPU_COMMON_H__ |
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#include <stddef.h> |
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#include "system/types.h" |
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typedef union Vector_t { |
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uint64 d[2]; |
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sint64 sd[2]; |
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float f[4]; |
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uint32 w[4]; |
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sint32 sw[4]; |
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uint16 h[8]; |
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sint16 sh[8]; |
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uint8 b[16]; |
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sint8 sb[16]; |
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} Vector_t; |
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/* |
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cr: .67 |
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0- 3 cr0 |
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4- 7 cr1 |
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8-11 cr2 |
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12-15 cr3 |
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16-19 cr4 |
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20-23 cr5 |
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24-27 cr6 |
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28-31 cr7 |
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*/ |
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#define CR_CR0(v) ((v)>>28) |
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#define CR_CR1(v) (((v)>>24)&0xf) |
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#define CR_CRx(v, x) (((v)>>(4*(7-(x))))&0xf) |
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/* |
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cr0 bits: .68 |
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lt |
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gt |
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eq |
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so |
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*/ |
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#define CR_CR0_LT (1<<31) |
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#define CR_CR0_GT (1<<30) |
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#define CR_CR0_EQ (1<<29) |
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#define CR_CR0_SO (1<<28) |
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/* |
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cr1 bits: .68 |
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4 Floating-point exception (FX) |
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5 Floating-point enabled exception (FEX) |
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6 Floating-point invalid exception (VX) |
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7 Floating-point overflow exception (OX) |
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*/ |
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#define CR_CR1_FX (1<<27) |
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#define CR_CR1_FEX (1<<26) |
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#define CR_CR1_VX (1<<25) |
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#define CR_CR1_OX (1<<24) |
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/* |
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FPSCR bits: .70 |
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*/ |
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#define FPSCR_FX (1<<31) |
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#define FPSCR_FEX (1<<30) |
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#define FPSCR_VX (1<<29) |
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#define FPSCR_OX (1<<28) |
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#define FPSCR_UX (1<<27) |
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#define FPSCR_ZX (1<<26) |
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#define FPSCR_XX (1<<25) |
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#define FPSCR_VXSNAN (1<<24) |
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#define FPSCR_VXISI (1<<23) |
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#define FPSCR_VXIDI (1<<22) |
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#define FPSCR_VXZDZ (1<<21) |
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#define FPSCR_VXIMZ (1<<20) |
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#define FPSCR_VXVC (1<<19) |
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#define FPSCR_FR (1<<18) |
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#define FPSCR_FI (1<<17) |
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#define FPSCR_FPRF(v) (((v)>>12)&0x1f) |
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#define FPSCR_res0 (1<<11) |
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#define FPSCR_VXSOFT (1<<10) |
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#define FPSCR_VXSQRT (1<<9) |
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#define FPSCR_VXCVI (1<<8) |
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#define FPSCR_VXVE (1<<7) |
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#define FPSCR_VXOE (1<<6) |
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#define FPSCR_VXUE (1<<5) |
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#define FPSCR_VXZE (1<<4) |
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#define FPSCR_VXXE (1<<3) |
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#define FPSCR_VXNI (1<<2) |
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#define FPSCR_RN(v) ((v)&3) |
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#define FPSCR_RN_NEAR 0 |
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#define FPSCR_RN_ZERO 1 |
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#define FPSCR_RN_PINF 2 |
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#define FPSCR_RN_MINF 3 |
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/* |
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VSCR bits: |
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sat = summary saturation |
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nj = non-java floating-point mode |
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*/ |
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#define VSCR_SAT 1 |
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#define VSCR_NJ (1<<16) |
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/* |
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xer bits: |
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0 so |
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1 ov |
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2 carry |
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3-24 res |
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25-31 number of bytes for lswx/stswx |
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*/ |
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#define XER_SO (1<<31) |
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#define XER_OV (1<<30) |
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#define XER_CA (1<<29) |
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#define XER_n(v) ((v)&0x7f) |
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/* |
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msr: .83 |
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0-12 res |
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13 POW power management enabled |
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14 res |
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15 ILE exception little-endian mode |
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16 EE enable external interrupt |
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17 PR privilege level (0=sv) |
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18 FP floating point avail |
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19 ME maschine check exception enable |
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20 FE0 floation point exception mode 0 |
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21 SE single step enable |
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22 BE branch trace enable |
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23 FE1 floation point exception mode 1 |
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24 res |
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25 IP exception prefix |
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26 IR intruction address translation |
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27 DR data address translation |
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28-29res |
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30 RI recoverable exception |
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31 LE little endian mode |
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*/ |
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#define MSR_UNKNOWN (1<<30) |
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#define MSR_UNKNOWN2 (1<<27) |
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#define MSR_VEC (1<<25) |
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#define MSR_KEY (1<<19) // 603e |
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#define MSR_POW (1<<18) |
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#define MSR_TGPR (1<<15) // 603(e) |
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#define MSR_ILE (1<<16) |
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#define MSR_EE (1<<15) |
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#define MSR_PR (1<<14) |
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#define MSR_FP (1<<13) |
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#define MSR_ME (1<<12) |
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#define MSR_FE0 (1<<11) |
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#define MSR_SE (1<<10) |
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#define MSR_BE (1<<9) |
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#define MSR_FE1 (1<<8) |
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#define MSR_IP (1<<6) |
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#define MSR_IR (1<<5) |
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#define MSR_DR (1<<4) |
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#define MSR_PM (1<<2) |
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#define MSR_RI (1<<1) |
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#define MSR_LE (1<<0) |
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//#define PPC_CPU_UNSUPPORTED_MSR_BITS (/*MSR_POW|*/MSR_ILE|MSR_BE|MSR_IP|MSR_LE) |
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#define PPC_CPU_UNSUPPORTED_MSR_BITS (~(MSR_POW | MSR_UNKNOWN | MSR_UNKNOWN2 | MSR_VEC | MSR_EE | MSR_PR | MSR_FP | MSR_ME | MSR_FE0 | MSR_SE | MSR_FE1 | MSR_IR | MSR_DR | MSR_RI)) |
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#define MSR_RFI_SAVE_MASK (0x87c0ff73) // was ff73 |
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/* |
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BAT Register: .88 |
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upper: |
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0-14 BEPI Block effective page index. |
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15-18 res |
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19-29 BL Block length. |
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30 Vs Supervisor mode valid bit. |
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31 Vp User mode valid bit. |
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lower: |
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0-14 BRPN This field is used in conjunction with the BL field to generate highorder bits of the physical address of the block. |
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15-24 res |
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25-28 WIMG Memory/cache access mode bits |
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29 res |
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30-31 PP Protection bits for block. |
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BAT Area |
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Length BL Encoding |
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128 Kbytes 000 0000 0000 |
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256 Kbytes 000 0000 0001 |
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512 Kbytes 000 0000 0011 |
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1 Mbyte 000 0000 0111 |
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2 Mbytes 000 0000 1111 |
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4 Mbytes 000 0001 1111 |
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8 Mbytes 000 0011 1111 |
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16 Mbytes 000 0111 1111 |
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32 Mbytes 000 1111 1111 |
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64 Mbytes 001 1111 1111 |
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128 Mbytes 011 1111 1111 |
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256 Mbytes 111 1111 1111 |
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*/ |
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#define BATU_BEPI(v) ((v)&0xfffe0000) |
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#define BATU_BL(v) (((v)&0x1ffc)>>2) |
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#define BATU_Vs (1<<1) |
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#define BATU_Vp (1) |
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#define BATL_BRPN(v) ((v)&0xfffe0000) |
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#define BAT_EA_OFFSET(v) ((v)&0x1ffff) |
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#define BAT_EA_11(v) ((v)&0x0ffe0000) |
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#define BAT_EA_4(v) ((v)&0xf0000000) |
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/* |
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sdr1: .91 |
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0-15 The high-order 16 bits of the 32-bit physical address of the page table |
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16-22 res |
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23-31 Mask for page table address |
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*/ |
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#define SDR1_HTABORG(v) (((v)>>16)&0xffff) |
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#define SDR1_HTABMASK(v) ((v)&0x1ff) |
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#define SDR1_PAGETABLE_BASE(v) ((v)&0xffff) |
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/* |
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sr: .94 |
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0 T=0: |
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1 Ks sv prot |
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2 Kp user prot |
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3 N No execute |
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4-7 res |
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8-31 VSID Virtual Segment ID |
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0 T=1: |
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1 Ks |
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2 Kp |
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3-11 BUID Bus Unit ID |
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12-31 CNTRL_SPEC |
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*/ |
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#define SR_T (1<<31) |
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#define SR_Ks (1<<30) |
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#define SR_Kp (1<<29) |
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#define SR_N (1<<28) |
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#define SR_VSID(v) ((v)&0xffffff) |
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#define SR_BUID(v) (((v)>>20)&0x1ff) |
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#define SR_CNTRL_SPEC(v) ((v)&0xfffff) |
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#define EA_SR(v) (((v)>>28)&0xf) |
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#define EA_PageIndex(v) (((v)>>12)&0xffff) |
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#define EA_Offset(v) ((v)&0xfff) |
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#define EA_API(v) (((v)>>22)&0x3f) |
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#define PA_RPN(v) (((v)>>12)&0xfffff) |
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#define PA_Offset(v) ((v)&0xfff) |
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/* |
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PTE: .364 |
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0 V |
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1-24 VSID |
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25 H |
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26-31 API |
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*/ |
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#define PTE1_V (1<<31) |
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#define PTE1_VSID(v) (((v)>>7)&0xffffff) |
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#define PTE1_H (1<<6) |
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#define PTE1_API(v) ((v)&0x3f) |
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#define PTE2_RPN(v) ((v)&0xfffff000) |
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#define PTE2_R (1<<8) |
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#define PTE2_C (1<<7) |
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#define PTE2_WIMG(v) (((v)>>3)&0xf) |
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#define PTE2_PP(v) ((v)&3) |
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#define PPC_L1_CACHE_LINE_SIZE 32 |
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#define PPC_LG_L1_CACHE_LINE_SIZE 5 |
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#define PPC_MAX_L1_COPY_PREFETCH 4 |
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/* |
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* special registers |
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*/ |
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#define HID0 1008 /* Checkstop and misc enables */ |
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#define HID1 1009 /* Clock configuration */ |
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#define IABR 1010 /* Instruction address breakpoint register */ |
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#define ICTRL 1011 /* Instruction Cache Control */ |
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#define LDSTDB 1012 /* Load/Store Debug */ |
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#define DABR 1013 /* Data address breakpoint register */ |
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#define MSSCR0 1014 /* Memory subsystem control */ |
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#define MSSCR1 1015 /* Memory subsystem debug */ |
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#define MSSSR0 1015 /* Memory Subsystem Status */ |
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#define LDSTCR 1016 /* Load/Store Status/Control */ |
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#define L2CR2 1016 /* L2 Cache control 2 */ |
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#define L2CR 1017 /* L2 Cache control */ |
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#define L3CR 1018 /* L3 Cache control */ |
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#define ICTC 1019 /* I-cache throttling control */ |
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#define THRM1 1020 /* Thermal management 1 */ |
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#define THRM2 1021 /* Thermal management 2 */ |
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#define THRM3 1022 /* Thermal management 3 */ |
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#define PIR 1023 /* Processor ID Register */ |
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//; hid0 bits |
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#define HID0_emcp 0 |
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#define HID0_emcpm 0x80000000 |
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#define HID0_dbp 1 |
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#define HID0_dbpm 0x40000000 |
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#define HID0_eba 2 |
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#define HID0_ebam 0x20000000 |
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#define HID0_ebd 3 |
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#define HID0_ebdm 0x10000000 |
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#define HID0_sbclk 4 |
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#define HID0_sbclkm 0x08000000 |
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#define HID0_eclk 6 |
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#define HID0_eclkm 0x02000000 |
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#define HID0_par 7 |
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#define HID0_parm 0x01000000 |
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#define HID0_sten 7 |
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#define HID0_stenm 0x01000000 |
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#define HID0_doze 8 |
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#define HID0_dozem 0x00800000 |
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#define HID0_nap 9 |
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#define HID0_napm 0x00400000 |
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#define HID0_sleep 10 |
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#define HID0_sleepm 0x00200000 |
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#define HID0_dpm 11 |
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#define HID0_dpmm 0x00100000 |
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#define HID0_riseg 12 |
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#define HID0_risegm 0x00080000 |
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#define HID0_eiec 13 |
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#define HID0_eiecm 0x00040000 |
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#define HID0_mum 14 |
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#define HID0_mumm 0x00020000 |
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#define HID0_nhr 15 |
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#define HID0_nhrm 0x00010000 |
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#define HID0_ice 16 |
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#define HID0_icem 0x00008000 |
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#define HID0_dce 17 |
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#define HID0_dcem 0x00004000 |
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#define HID0_ilock 18 |
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#define HID0_ilockm 0x00002000 |
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#define HID0_dlock 19 |
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#define HID0_dlockm 0x00001000 |
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#define HID0_icfi 20 |
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#define HID0_icfim 0x00000800 |
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#define HID0_dcfi 21 |
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#define HID0_dcfim 0x00000400 |
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#define HID0_spd 22 |
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#define HID0_spdm 0x00000200 |
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#define HID0_sge 24 |
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#define HID0_sgem 0x00000080 |
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#define HID0_dcfa 25 |
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#define HID0_dcfam 0x00000040 |
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#define HID0_btic 26 |
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#define HID0_bticm 0x00000020 |
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#define HID0_lrstk 27 |
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#define HID0_lrstkm 0x00000010 |
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#define HID0_abe 28 |
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#define HID0_abem 0x00000008 |
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#define HID0_fold 28 |
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#define HID0_foldm 0x00000008 |
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#define HID0_bht 29 |
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#define HID0_bhtm 0x00000004 |
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#define HID0_nopdst 30 |
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#define HID0_nopdstm 0x00000002 |
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#define HID0_nopti 31 |
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#define HID0_noptim 0x00000001 |
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#endif |
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