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/* |
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* Copyright (C) 2006-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_sh.c,v 1.18 2007/04/13 07:06:31 debug Exp $ |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "sh4_exception.h" |
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#include "sh4_mmu.h" |
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|
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|
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/* |
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* translate_via_mmu(): |
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* |
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* Scan the UTLB for a matching virtual address. If a match was found, then |
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* check permission bits etc. If everything was ok, then return the physical |
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* page address, otherwise cause an exception. |
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* |
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* The implementation should (hopefully) be quite complete, except for lack |
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* of "Multiple matching entries" detection. (On a real CPU, these would |
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* cause exceptions.) |
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* |
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* Same return values as sh_translate_v2p(). |
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*/ |
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static int translate_via_mmu(struct cpu *cpu, uint32_t vaddr, |
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uint64_t *return_paddr, int flags) |
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{ |
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int wf = flags & FLAG_WRITEFLAG; |
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int i, urb, urc, require_asid_match, cur_asid, expevt = 0; |
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uint32_t hi, lo = 0, mask = 0; |
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int sh; /* Shared */ |
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int d; /* Dirty bit */ |
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int v; /* Valid bit */ |
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int pr; /* Protection */ |
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int i_start; |
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|
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cur_asid = cpu->cd.sh.pteh & SH4_PTEH_ASID_MASK; |
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require_asid_match = !(cpu->cd.sh.mmucr & SH4_MMUCR_SV) |
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|| !(cpu->cd.sh.sr & SH_SR_MD); |
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|
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if (!(flags & FLAG_NOEXCEPTIONS)) { |
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/* |
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* Increase URC every time the UTLB is accessed. (Note: |
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* According to the SH4 manual, the URC should not be |
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* increased when running the ldtlb instruction. Perhaps this |
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* is a good place? Perhaps it is better to just set it to a |
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* random value? TODO: Find out. |
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*/ |
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urb = (cpu->cd.sh.mmucr & SH4_MMUCR_URB_MASK) >> |
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SH4_MMUCR_URB_SHIFT; |
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urc = (cpu->cd.sh.mmucr & SH4_MMUCR_URC_MASK) >> |
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SH4_MMUCR_URC_SHIFT; |
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|
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/* fatal("urc = %i ==> ", urc); */ |
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urc ++; |
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if (urc >= SH_N_UTLB_ENTRIES || (urb > 0 && urc == urb)) |
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urc = 0; |
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/* fatal("%i\n", urc); */ |
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|
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cpu->cd.sh.mmucr &= ~SH4_MMUCR_URC_MASK; |
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cpu->cd.sh.mmucr |= (urc << SH4_MMUCR_URC_SHIFT); |
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} |
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|
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/* |
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* When doing Instruction lookups, the ITLB should be scanned first. |
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* This is done by using negative i. (Ugly hack, but works.) |
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*/ |
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if (flags & FLAG_INSTR) |
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i_start = -SH_N_ITLB_ENTRIES; |
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else |
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i_start = 0; |
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|
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for (i=i_start; i<SH_N_UTLB_ENTRIES; i++) { |
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if (i<0) { |
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hi = cpu->cd.sh.itlb_hi[i + SH_N_ITLB_ENTRIES]; |
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lo = cpu->cd.sh.itlb_lo[i + SH_N_ITLB_ENTRIES]; |
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} else { |
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hi = cpu->cd.sh.utlb_hi[i]; |
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lo = cpu->cd.sh.utlb_lo[i]; |
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} |
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mask = 0xfff00000; |
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|
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v = lo & SH4_PTEL_V; |
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if (!v) |
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continue; |
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|
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switch (lo & SH4_PTEL_SZ_MASK) { |
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case SH4_PTEL_SZ_1K: mask = 0xfffffc00; break; |
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case SH4_PTEL_SZ_4K: mask = 0xfffff000; break; |
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case SH4_PTEL_SZ_64K: mask = 0xffff0000; break; |
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/* case SH4_PTEL_SZ_1M: mask = 0xfff00000; break; */ |
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} |
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|
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if ((hi & mask) != (vaddr & mask)) |
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continue; |
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|
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sh = lo & SH4_PTEL_SH; |
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|
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if (!sh && require_asid_match) { |
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int asid = hi & SH4_PTEH_ASID_MASK; |
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if (asid != cur_asid) |
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continue; |
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} |
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|
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/* Note/TODO: Check for multiple matches is not implemented. */ |
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|
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break; |
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} |
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|
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/* Virtual address not found? Then it's a TLB miss. */ |
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if (i == SH_N_UTLB_ENTRIES) |
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goto tlb_miss; |
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|
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/* Matching address found! Let's see whether it is |
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readable/writable, etc.: */ |
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d = lo & SH4_PTEL_D? 1 : 0; |
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pr = (lo & SH4_PTEL_PR_MASK) >> SH4_PTEL_PR_SHIFT; |
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|
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*return_paddr = (vaddr & ~mask) | (lo & mask & 0x1fffffff); |
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|
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if (flags & FLAG_INSTR) { |
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/* |
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* Instruction access: |
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* |
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* If a matching entry wasn't found in the ITLB, but in the |
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* UTLB, then copy it to a random place in the ITLB. |
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*/ |
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if (i >= 0) { |
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int r = random() % SH_N_ITLB_ENTRIES; |
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|
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/* NOTE: Make sure that the old mapping for |
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that itlb entry is invalidated: */ |
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cpu->invalidate_translation_caches(cpu, |
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cpu->cd.sh.itlb_hi[r] & ~0xfff, INVALIDATE_VADDR); |
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|
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cpu->invalidate_code_translation(cpu, |
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cpu->cd.sh.utlb_lo[i] & ~0xfff, INVALIDATE_PADDR); |
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|
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cpu->cd.sh.itlb_hi[r] = cpu->cd.sh.utlb_hi[i]; |
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cpu->cd.sh.itlb_lo[r] = cpu->cd.sh.utlb_lo[i]; |
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} |
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|
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/* Permission checks: */ |
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if (cpu->cd.sh.sr & SH_SR_MD) |
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return 1; |
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if (!(pr & 2)) |
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goto protection_violation; |
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|
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return 1; |
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} |
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|
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/* Data access: */ |
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if (cpu->cd.sh.sr & SH_SR_MD) { |
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/* Kernel access: */ |
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switch (pr) { |
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case 0: |
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case 2: if (wf) |
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goto protection_violation; |
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return 1; |
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case 1: |
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case 3: if (wf && !d) |
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goto initial_write_exception; |
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return 1 + d; |
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} |
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} |
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|
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/* User access */ |
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switch (pr) { |
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case 0: |
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case 1: goto protection_violation; |
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case 2: if (wf) |
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goto protection_violation; |
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return 1; |
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case 3: if (wf && !d) |
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goto initial_write_exception; |
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return 1 + d; |
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} |
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|
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|
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tlb_miss: |
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expevt = wf? EXPEVT_TLB_MISS_ST : EXPEVT_TLB_MISS_LD; |
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goto exception; |
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|
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protection_violation: |
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expevt = wf? EXPEVT_TLB_PROT_ST : EXPEVT_TLB_PROT_LD; |
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goto exception; |
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|
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initial_write_exception: |
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expevt = EXPEVT_TLB_MOD; |
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|
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|
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exception: |
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if (flags & FLAG_NOEXCEPTIONS) { |
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*return_paddr = 0; |
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return 2; |
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} |
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|
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sh_exception(cpu, expevt, 0, vaddr); |
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|
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return 0; |
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} |
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|
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|
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/* |
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* sh_translate_v2p(): |
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* |
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* Return values: |
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* |
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* 0 No access to the virtual address. |
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* 1 return_paddr contains the physical address, the page is |
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* available as read-only. |
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* 2 Same as 1, but the page is available as read/write. |
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*/ |
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int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr, uint64_t *return_paddr, |
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int flags) |
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{ |
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int user = cpu->cd.sh.sr & SH_SR_MD? 0 : 1; |
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|
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vaddr = (uint32_t)vaddr; |
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|
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/* U0/P0: Userspace addresses, or P3: Kernel virtual memory. */ |
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if (!(vaddr & 0x80000000) || |
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(vaddr >= 0xc0000000 && vaddr < 0xe0000000)) { |
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/* Address translation turned off? */ |
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if (!(cpu->cd.sh.mmucr & SH4_MMUCR_AT)) { |
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/* Then return raw physical address: */ |
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*return_paddr = vaddr & 0x1fffffff; |
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return 2; |
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} |
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|
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/* Perform translation via the MMU: */ |
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return translate_via_mmu(cpu, vaddr, return_paddr, flags); |
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} |
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|
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/* Store queue region: */ |
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if (vaddr >= 0xe0000000 && vaddr < 0xe4000000) { |
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/* Note/TODO: Take SH4_MMUCR_SQMD into account. */ |
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*return_paddr = vaddr; |
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return 2; |
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} |
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|
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if (user) { |
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if (flags & FLAG_NOEXCEPTIONS) { |
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*return_paddr = 0; |
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return 2; |
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} |
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|
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fatal("Userspace tried to access non-user space memory." |
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" TODO: cause exception! (vaddr=0x%08"PRIx32"\n", |
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(uint32_t) vaddr); |
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exit(1); |
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} |
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|
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/* P1,P2: Direct-mapped physical memory. */ |
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if (vaddr >= 0x80000000 && vaddr < 0xc0000000) { |
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*return_paddr = vaddr & 0x1fffffff; |
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return 2; |
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} |
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|
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if (flags & FLAG_INSTR) { |
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fatal("TODO: instr at 0x%08"PRIx32"\n", (uint32_t)vaddr); |
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exit(1); |
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} |
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|
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/* P4: Special registers mapped at 0xf0000000 .. 0xffffffff: */ |
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if ((vaddr & 0xf0000000) == 0xf0000000) { |
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*return_paddr = vaddr; |
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return 2; |
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} |
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|
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if (flags & FLAG_NOEXCEPTIONS) { |
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*return_paddr = 0; |
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return 2; |
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} |
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|
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/* TODO */ |
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fatal("Unimplemented SH vaddr 0x%08"PRIx32"\n", (uint32_t)vaddr); |
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exit(1); |
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|
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return 0; |
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} |
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