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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_8253.c,v 1.18 2006/12/30 13:30:57 debug Exp $ |
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* |
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* Intel 8253/8254 Programmable Interval Timer |
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* |
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* TODO/NOTE: |
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* The timers don't really count down. Timer 0 causes clock interrupts |
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* at a specific frequency, but reading the counter register would not |
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* result in anything meaningful. |
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* |
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* (Split counter[] into reset value and current value.) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "emul.h" |
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#include "interrupt.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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#include "timer.h" |
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|
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#include "i8253reg.h" |
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|
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|
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#define debug fatal |
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|
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#define DEV_8253_LENGTH 4 |
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#define TICK_SHIFT 14 |
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|
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|
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struct pit8253_data { |
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int in_use; |
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|
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int counter_select; |
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uint8_t mode_byte; |
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|
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int mode[3]; |
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int counter[3]; |
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|
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int hz[3]; |
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|
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struct timer *timer0; |
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struct interrupt irq; |
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int pending_interrupts_timer0; |
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}; |
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|
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|
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static void timer0_tick(struct timer *t, void *extra) |
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{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
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d->pending_interrupts_timer0 ++; |
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|
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#if 0 |
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printf("%i ", d->pending_interrupts_timer0); fflush(stdout); |
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#endif |
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} |
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|
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|
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DEVICE_TICK(8253) |
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{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
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|
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if (!d->in_use) |
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return; |
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|
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switch (d->mode[0] & 0x0e) { |
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|
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case I8253_TIMER_INTTC: |
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if (d->pending_interrupts_timer0 > 0) |
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INTERRUPT_ASSERT(d->irq); |
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break; |
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|
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case I8253_TIMER_SQWAVE: |
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case I8253_TIMER_RATEGEN: |
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break; |
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|
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default:fatal("[ 8253: unimplemented mode 0x%x ]\n", d->mode[0] & 0x0e); |
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exit(1); |
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} |
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} |
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|
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|
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DEVICE_ACCESS(8253) |
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{ |
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struct pit8253_data *d = (struct pit8253_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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|
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if (writeflag == MEM_WRITE) |
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idata = memory_readmax64(cpu, data, len); |
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|
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d->in_use = 1; |
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|
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switch (relative_addr) { |
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|
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case I8253_TIMER_CNTR0: |
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case I8253_TIMER_CNTR1: |
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case I8253_TIMER_CNTR2: |
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if (writeflag == MEM_WRITE) { |
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switch (d->mode_byte & 0x30) { |
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case I8253_TIMER_LSB: |
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case I8253_TIMER_16BIT: |
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d->counter[relative_addr] &= 0xff00; |
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d->counter[relative_addr] |= (idata & 0xff); |
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break; |
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case I8253_TIMER_MSB: |
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d->counter[relative_addr] &= 0x00ff; |
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d->counter[relative_addr] |= ((idata&0xff)<<8); |
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if (d->counter[relative_addr] != 0) |
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d->hz[relative_addr] = |
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I8253_TIMER_FREQ / (float) |
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d->counter[relative_addr] + 0.5; |
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else |
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d->hz[relative_addr] = 0; |
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debug("[ 8253: counter %i set to %i (%i Hz) " |
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"]\n", relative_addr, d->counter[ |
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relative_addr], d->hz[relative_addr]); |
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switch (relative_addr) { |
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case 0: if (d->timer0 == NULL) |
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d->timer0 = timer_add( |
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d->hz[0], timer0_tick, d); |
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else |
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timer_update_frequency( |
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d->timer0, d->hz[0]); |
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break; |
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case 1: fatal("TODO: DMA refresh?\n"); |
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exit(1); |
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case 2: fatal("TODO: 8253 tone generation?\n"); |
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break; |
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} |
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break; |
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default:fatal("[ 8253: huh? writing to counter" |
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" %i but neither from msb nor lsb? ]\n", |
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relative_addr); |
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} |
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} else { |
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switch (d->mode_byte & 0x30) { |
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case I8253_TIMER_LSB: |
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case I8253_TIMER_16BIT: |
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odata = d->counter[relative_addr] & 0xff; |
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break; |
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case I8253_TIMER_MSB: |
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odata = (d->counter[relative_addr] >> 8) & 0xff; |
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break; |
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default:fatal("[ 8253: huh? reading from counter" |
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" %i but neither from msb nor lsb? ]\n", |
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relative_addr); |
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} |
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} |
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|
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/* Switch from LSB to MSB, if accessing as 16-bit word: */ |
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if ((d->mode_byte & 0x30) == I8253_TIMER_16BIT) |
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d->mode_byte &= ~I8253_TIMER_LSB; |
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|
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break; |
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|
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case I8253_TIMER_MODE: |
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if (writeflag == MEM_WRITE) { |
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d->mode_byte = idata; |
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|
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d->counter_select = idata >> 6; |
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if (d->counter_select > 2) { |
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debug("[ 8253: attempt to select counter 3," |
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" which doesn't exist. ]\n"); |
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d->counter_select = 0; |
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} |
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|
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d->mode[d->counter_select] = idata & 0x0e; |
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|
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debug("[ 8253: select=%i mode=0x%x ", |
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d->counter_select, d->mode[d->counter_select]); |
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if (idata & 0x30) { |
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switch (idata & 0x30) { |
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case I8253_TIMER_LSB: |
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debug("LSB "); |
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break; |
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case I8253_TIMER_16BIT: |
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debug("LSB+"); |
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case I8253_TIMER_MSB: |
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debug("MSB "); |
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} |
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} |
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debug("]\n"); |
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|
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if (idata & I8253_TIMER_BCD) { |
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fatal("[ 8253: BCD not yet implemented ]\n"); |
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exit(1); |
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} |
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} else { |
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debug("[ 8253: read; can this actually happen? ]\n"); |
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odata = d->mode_byte; |
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} |
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break; |
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|
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default:if (writeflag == MEM_WRITE) { |
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fatal("[ 8253: unimplemented write to address 0x%x" |
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" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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} else { |
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fatal("[ 8253: unimplemented read from address 0x%x " |
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"]\n", (int)relative_addr); |
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} |
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exit(1); |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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DEVINIT(8253) |
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{ |
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struct pit8253_data *d = malloc(sizeof(struct pit8253_data)); |
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|
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct pit8253_data)); |
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|
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d->in_use = devinit->in_use; |
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|
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INTERRUPT_CONNECT(devinit->interrupt_path, d->irq); |
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|
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/* Don't cause interrupt, by default. */ |
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d->mode[0] = I8253_TIMER_RATEGEN; |
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d->mode[1] = I8253_TIMER_RATEGEN; |
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d->mode[2] = I8253_TIMER_RATEGEN; |
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|
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devinit->machine->isa_pic_data.pending_timer_interrupts = |
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&d->pending_interrupts_timer0; |
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|
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memory_device_register(devinit->machine->memory, devinit->name, |
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devinit->addr, DEV_8253_LENGTH, dev_8253_access, (void *)d, |
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DM_DEFAULT, NULL); |
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|
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machine_add_tickfunction(devinit->machine, dev_8253_tick, |
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d, TICK_SHIFT, 0.0); |
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|
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return 1; |
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} |
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