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dpavlin |
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/* gxemul: $Id: dec_maxine.h,v 1.3 2005/03/05 12:34:02 debug Exp $ */ |
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/* $NetBSD: maxine.h,v 1.8 2000/02/29 04:41:57 nisimura Exp $ */ |
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/*- |
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* Copyright (c) 1992, 1993 |
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* The Regents of the University of California. All rights reserved. |
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* |
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* This code is derived from software contributed to Berkeley by |
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* The Mach Operating System project at Carnegie-Mellon University, |
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* Ralph Campbell and Rick Macklem. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the University of |
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* California, Berkeley and its contributors. |
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* 4. Neither the name of the University nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* @(#)maxine.h 8.1 (Berkeley) 6/10/93 |
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*/ |
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/* |
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* Mach Operating System |
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* Copyright (c) 1991,1990,1989 Carnegie Mellon University |
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* All Rights Reserved. |
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* |
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* Permission to use, copy, modify and distribute this software and |
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* its documentation is hereby granted, provided that both the copyright |
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* notice and this permission notice appear in all copies of the |
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* software, derivative works or modified versions, and any portions |
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* thereof, and that both notices appear in supporting documentation. |
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* |
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND |
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
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* |
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* Carnegie Mellon requests users of this software to return to |
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* |
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
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* School of Computer Science |
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* Carnegie Mellon University |
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* Pittsburgh PA 15213-3890 |
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* |
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* any improvements or extensions that they make and grant Carnegie the |
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* rights to redistribute these changes. |
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*/ |
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/* |
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* HISTORY |
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* Log: maxine.h,v |
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* Revision 2.3 92/04/01 15:14:52 rpd |
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* Defined pseudo slot for mappable timer. |
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* [92/03/11 02:37:41 af] |
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* |
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* Revision 2.2 92/03/02 18:34:28 rpd |
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* Created, from the DEC specs: |
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* "MAXine System Module Functional Specification" Revision 1.2 |
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* Workstation Systems Engineering, Palo Alto, CA. July 15, 1991. |
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* [92/01/17 af] |
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* |
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*/ |
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/* |
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* File: maxine.h |
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* Author: Alessandro Forin, Carnegie Mellon University |
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* Date: 1/92 |
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* |
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* Definitions specific to the MAXine system module (54-21325-01) |
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* and compatible processors (KN02BA). |
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*/ |
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#ifndef MIPS_XINE_H |
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#define MIPS_XINE_H 1 |
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/* |
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* MAXine's Physical address space |
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*/ |
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#define XINE_PHYS_MIN 0x00000000 /* 512 Meg */ |
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#define XINE_PHYS_MAX 0x1fffffff |
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/* |
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* Memory map |
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*/ |
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#define XINE_PHYS_MEMORY_START 0x00000000 |
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#define XINE_PHYS_MEMORY_END 0x027fffff /* 40 Meg in 2 slots |
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and baseboard */ |
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/* |
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* I/O map |
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*/ |
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#define XINE_PHYS_CFB_START 0x08000000 /* Color Frame Buffer */ |
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#define XINE_PHYS_CFB_END 0x0bffffff /* 64 Meg */ |
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#define XINE_PHYS_MREGS_START 0x0c000000 /* Memory control registers */ |
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#define XINE_PHYS_MREGS_END 0x0dffffff /* 32 Meg */ |
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#define XINE_PHYS_CREGS_START 0x0e000000 /* CPU ASIC control regs */ |
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#define XINE_PHYS_CREGS_END 0x0fffffff /* 32 Meg */ |
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#define XINE_PHYS_TC_0_START 0x10000000 /* TURBOchannel, slot 0 */ |
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#define XINE_PHYS_TC_0_END 0x13ffffff /* 64 Meg, option0 */ |
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#define XINE_PHYS_TC_1_START 0x14000000 /* TURBOchannel, slot 1 */ |
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#define XINE_PHYS_TC_1_END 0x17ffffff /* 64 Meg, option1 */ |
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#define XINE_PHYS_TC_RESERVED 0x18000000 /* Unused slot 2 */ |
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/* 64 Meg */ |
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#define XINE_PHYS_TC_3_START 0x1c000000 /* TURBOchannel, slot 3 */ |
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#define XINE_PHYS_TC_3_END 0x1fffffff /* 64 Meg, system devices */ |
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#define XINE_PHYS_TC_START XINE_PHYS_TC_0_START |
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#define XINE_PHYS_TC_END XINE_PHYS_TC_3_END /* 256 Meg */ |
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#define XINE_TC_NSLOTS 4 |
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#define XINE_TC_MIN 0 |
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#define XINE_TC_MAX 1 /* only option slots */ |
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/* |
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* System module space |
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*/ |
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#define XINE_SYS_ASIC (XINE_PHYS_TC_3_START + 0x0000000) |
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#define XINE_SYS_ROM_START (XINE_SYS_ASIC + IOASIC_SLOT_0_START) |
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#define XINE_SYS_ASIC_REGS (XINE_SYS_ASIC + IOASIC_SLOT_1_START) |
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#define XINE_SYS_ETHER_ADDRESS (XINE_SYS_ASIC + IOASIC_SLOT_2_START) |
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#define XINE_SYS_LANCE (XINE_SYS_ASIC + IOASIC_SLOT_3_START) |
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#define XINE_SYS_SCC_0 (XINE_SYS_ASIC + IOASIC_SLOT_4_START) |
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#define XINE_SYS_VDAC_HI (XINE_SYS_ASIC + IOASIC_SLOT_5_START) |
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#define XINE_SYS_VDAC_LO (XINE_SYS_ASIC + IOASIC_SLOT_7_START) |
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#define XINE_SYS_CLOCK (XINE_SYS_ASIC + IOASIC_SLOT_8_START) |
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#define XINE_SYS_ISDN (XINE_SYS_ASIC + IOASIC_SLOT_9_START) |
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#define XINE_SYS_DTOP (XINE_SYS_ASIC + IOASIC_SLOT_10_START) |
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#define XINE_SYS_FLOPPY (XINE_SYS_ASIC + IOASIC_SLOT_11_START) |
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#define XINE_SYS_SCSI (XINE_SYS_ASIC + IOASIC_SLOT_12_START) |
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#define XINE_SYS_FLOPPY_DMA (XINE_SYS_ASIC + IOASIC_SLOT_13_START) |
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#define XINE_SYS_SCSI_DMA (XINE_SYS_ASIC + IOASIC_SLOT_14_START) |
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#define XINE_SYS_BOOT_ROM_START (XINE_PHYS_TC_3_START + 0x3c00000) |
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#define XINE_SYS_BOOT_ROM_END (XINE_PHYS_TC_3_START + 0x3c40000) |
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/* |
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* Interrupts |
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*/ |
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#define XINE_INT_FPA IP_LEV7 /* Floating Point coproc */ |
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#define XINE_INT_HALTB IP_LEV6 /* Halt keycode (DTOP) */ |
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#define XINE_INT_TC3 IP_LEV5 /* TC slot 3, system */ |
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#define XINE_INT_TIMEOUT IP_LEV4 /* Timeout on I/O write */ |
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#define XINE_INT_TOY IP_LEV3 /* Clock chip */ |
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#define XINE_INT_1_10_MS IP_LEV2 /* Periodic interrupt */ |
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/* |
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* System registers addresses (MREG and CREG space, and IO Control ASIC) |
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*/ |
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#define XINE_REG_CMR 0x0c000000 /* Color mask register */ |
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#define XINE_REG_MER 0x0c400000 /* Memory error register */ |
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#define XINE_REG_MSR 0x0c800000 /* Memory size register */ |
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#define XINE_REG_FCTR 0x0ca00000 /* 1us free running counter */ |
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#define XINE_REG_FI 0x0cc00000 /* FI signal polarity (1!) */ |
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#define XINE_REG_CNFG 0x0e000000 /* Config mem timeouts */ |
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#define XINE_REG_AER 0x0e000004 /* Address error register */ |
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#define XINE_REG_TIMEOUT 0x0e00000c /* I/O write timeout reg */ |
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#define XINE_REG_SCSI_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCSI_DMAPTR ) |
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#define XINE_REG_SCSI_DMANPTR ( XINE_SYS_ASIC + IOASIC_SCSI_NEXTPTR ) |
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#define XINE_REG_LANCE_DMAPTR ( XINE_SYS_ASIC + IOASIC_LANCE_DMAPTR ) |
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#define XINE_REG_SCC_T1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T1_DMAPTR ) |
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#define XINE_REG_SCC_R1_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R1_DMAPTR ) |
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#define XINE_REG_DTOP_T_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_T2_DMAPTR ) |
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#define XINE_REG_DTOP_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_SCC_R2_DMAPTR ) |
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#define XINE_FLOPPY_DMAPTR ( XINE_SYS_ASIC + IOASIC_FLOPPY_DMAPTR ) |
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#define XINE_ISDN_X_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_DMAPTR ) |
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#define XINE_ISDN_X_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_X_NEXTPTR ) |
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#define XINE_ISDN_R_DMAPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_DMAPTR ) |
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#define XINE_ISDN_R_NEXTPTR ( XINE_SYS_ASIC + IOASIC_ISDN_R_NEXTPTR ) |
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#define XINE_REG_CSR ( XINE_SYS_ASIC + IOASIC_CSR ) |
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#define XINE_REG_INTR ( XINE_SYS_ASIC + IOASIC_INTR ) |
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#define XINE_REG_IMSK ( XINE_SYS_ASIC + IOASIC_IMSK ) |
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#define XINE_REG_CURADDR ( XINE_SYS_ASIC + IOASIC_CURADDR ) |
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#define XINE_ISDN_X_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_X_DATA ) |
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#define XINE_ISDN_R_DATA ( XINE_SYS_ASIC + IOASIC_ISDN_R_DATA ) |
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#define XINE_REG_LANCE_DECODE ( XINE_SYS_ASIC + IOASIC_LANCE_DECODE ) |
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#define XINE_REG_SCSI_DECODE ( XINE_SYS_ASIC + IOASIC_SCSI_DECODE ) |
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#define XINE_REG_SCC0_DECODE ( XINE_SYS_ASIC + IOASIC_SCC0_DECODE ) |
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#define XINE_REG_DTOP_DECODE ( XINE_SYS_ASIC + IOASIC_SCC1_DECODE ) |
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#define XINE_REG_FLOPPY_DECODE ( XINE_SYS_ASIC + IOASIC_FLOPPY_DECODE ) |
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# define XINE_LANCE_CONFIG 3 |
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# define XINE_SCSI_CONFIG 14 |
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# define XINE_SCC0_CONFIG (0x10|4) |
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# define XINE_DTOP_CONFIG 10 |
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# define XINE_FLOPPY_CONFIG 13 |
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#define XINE_REG_SCSI_SCR ( XINE_SYS_ASIC + IOASIC_SCSI_SCR ) |
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#define XINE_REG_SCSI_SDR0 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR0 ) |
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#define XINE_REG_SCSI_SDR1 ( XINE_SYS_ASIC + IOASIC_SCSI_SDR1 ) |
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/* |
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* System registers defines (MREG and CREG) |
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*/ |
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/* Memory error register */ |
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#define XINE_MER_xxx 0xf7fe30ff /* undefined */ |
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#define XINE_MER_10_1_MS_IP 0x08000000 /* rw: Periodic interrupt */ |
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#define XINE_MER_PAGE_BRY 0x00010000 /* rw: Page boundary error */ |
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#define XINE_MER_TLEN 0x00008000 /* rw: Xfer length error */ |
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#define XINE_MER_PARDIS 0x00004000 /* rw: Dis parity err intr */ |
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#define XINE_MER_LASTBYTE 0x00000f00 /* rz: Last byte in error: */ |
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# define XINE_LASTB31 0x00000800 /* upper byte of word */ |
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# define XINE_LASTB23 0x00000400 /* .. through .. */ |
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# define XINE_LASTB15 0x00000200 /* .. the .. */ |
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# define XINE_LASTB07 0x00000100 /* .. lower byte */ |
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/* Memory size register */ |
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#define XINE_MSR_xxx 0xffffdfff /* undefined */ |
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#define XINE_MSR_10_1_MS_EN 0x04000000 /* rw: enable periodic intr */ |
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#define XINE_MSR_10_1_MS 0x02000000 /* rw: intr. freq. (0->1ms) */ |
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#define XINE_MSR_PFORCE 0x01e00000 /* rw: force parity errors */ |
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#define XINE_MSR_MABEN 0x00100000 /* rw: VRAM ignores SIZE */ |
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#define XINE_MSR_LAST_BANK 0x000e0000 /* rw: map baseboard mem */ |
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# define XINE_BANK_0 0x00020000 /* .. at bank 0, .. */ |
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# define XINE_BANK_1 0x00040000 /* .. at bank 1, .. */ |
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# define XINE_BANK_2 0x00080000 /* .. or at bank 2 */ |
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#define XINE_MSR_SIZE_16Mb 0x00002000 /* rw: using 16Mb mem banks */ |
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/* FI register */ |
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#define XINE_FI_VALUE 0x00001000 |
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/* NOTES |
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Memory access priority is, from higher to lower: |
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- VRAM/DRAM refresh |
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- IO DMA (IO Control ASIC) |
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- Slot 0 DMA |
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- Processor |
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- Slot 1 DMA |
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Memory performance is (with 80ns mem cycles) |
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- single word read 5 cyc 10.0 Mb/s |
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- word write 3 cyc 16.7 Mb/s |
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- single byte write 3 cyc 4.2 Mb/s |
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- 64w DMA read 68 cyc 47.1 Mb/s |
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- 64w DMA write 66 cyc 48.5 Mb/s |
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- Refresh 5 cyc N/A |
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*/ |
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/* Timeout config register */ |
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#define XINE_CNFG_VALUE 121 |
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/* Address error register */ |
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#define XINE_AER_ADDR_MASK 0x1ffffffc /* ro: phys addr in error */ |
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/* Memory access timeout interrupt register */ |
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#define XINE_TIMEO_INTR 0x00000001 /* rc: intr pending */ |
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/* |
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* More system registers defines (IO Control ASIC) |
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*/ |
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/* (re)defines for the system Status and Control register (SSR) */ |
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/* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ |
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#define XINE_CSR_DIAGDN 0x00008000 /* rw */ |
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#define XINE_CSR_ISDN_ENABLE 0x00001000 /* rw */ |
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#define XINE_CSR_SCC_ENABLE 0x00000800 /* rw */ |
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#define XINE_CSR_RTC_ENABLE 0x00000400 /* rw */ |
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#define XINE_CSR_SCSI_ENABLE 0x00000200 /* rw */ |
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#define XINE_CSR_LANCE_ENABLE 0x00000100 /* rw */ |
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#define XINE_CSR_FLOPPY_ENABLE 0x00000080 /* rw */ |
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#define XINE_CSR_VDAC_ENABLE 0x00000040 /* rw */ |
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#define XINE_CSR_DTOP_ENABLE 0x00000020 /* rw */ |
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#define XINE_CSR_LED 0x00000001 /* rw */ |
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/* (re)defines for the System Interrupt and Mask Registers */ |
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/* high-order 16 bits 0xFFFF0000 same on all DECstation IOASICs */ |
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#define XINE_INTR_xxxx 0x00002808 /* ro */ |
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#define XINE_INTR_FLOPPY 0x00008000 /* ro */ |
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#define XINE_INTR_NVR_JUMPER 0x00004000 /* ro */ |
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#define XINE_INTR_POWERUP 0x00002000 /* ro */ |
| 294 |
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#define XINE_INTR_TC_0 0x00001000 /* ro */ |
| 295 |
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#define XINE_INTR_ISDN 0x00000800 /* ro */ |
| 296 |
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#define XINE_INTR_NRMOD_JUMPER 0x00000400 /* ro */ |
| 297 |
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#define XINE_INTR_SCSI 0x00000200 /* ro */ |
| 298 |
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#define XINE_INTR_LANCE 0x00000100 /* ro */ |
| 299 |
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#define XINE_INTR_FLOPPY_HDS 0x00000080 /* ro */ |
| 300 |
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#define XINE_INTR_SCC_0 0x00000040 /* ro */ |
| 301 |
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#define XINE_INTR_TC_1 0x00000020 /* ro */ |
| 302 |
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#define XINE_INTR_FLOPPY_XDS 0x00000010 /* ro */ |
| 303 |
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#define XINE_INTR_VINT 0x00000008 /* ro */ |
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#define XINE_INTR_N_VINT 0x00000004 /* ro */ |
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#define XINE_INTR_DTOP_TX 0x00000002 /* ro */ |
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#define XINE_INTR_DTOP_RX 0x00000001 /* ro */ |
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#define XINE_INTR_ASIC 0xffff0000 |
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#define XINE_INTR_DTOP 0x00000003 |
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#define XINE_IM0 0xffff9b6b /* all good ones enabled */ |
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| 311 |
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#endif /* MIPS_XINE_H */ |
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