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/* |
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* Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm_instr_misc.c,v 1.6 2006/12/30 13:30:53 debug Exp $ |
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* |
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* Misc ARM instructions. Included from cpu_arm_instr.c. |
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*/ |
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|
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|
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/* |
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* clear_rX: Move #0 into a register. (Optimization hack.) |
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*/ |
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X(clear_r0) { cpu->cd.arm.r[ 0] = 0; } Y(clear_r0) |
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X(clear_r1) { cpu->cd.arm.r[ 1] = 0; } Y(clear_r1) |
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X(clear_r2) { cpu->cd.arm.r[ 2] = 0; } Y(clear_r2) |
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X(clear_r3) { cpu->cd.arm.r[ 3] = 0; } Y(clear_r3) |
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X(clear_r4) { cpu->cd.arm.r[ 4] = 0; } Y(clear_r4) |
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X(clear_r5) { cpu->cd.arm.r[ 5] = 0; } Y(clear_r5) |
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X(clear_r6) { cpu->cd.arm.r[ 6] = 0; } Y(clear_r6) |
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X(clear_r7) { cpu->cd.arm.r[ 7] = 0; } Y(clear_r7) |
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X(clear_r8) { cpu->cd.arm.r[ 8] = 0; } Y(clear_r8) |
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X(clear_r9) { cpu->cd.arm.r[ 9] = 0; } Y(clear_r9) |
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X(clear_r10) { cpu->cd.arm.r[10] = 0; } Y(clear_r10) |
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X(clear_r11) { cpu->cd.arm.r[11] = 0; } Y(clear_r11) |
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X(clear_r12) { cpu->cd.arm.r[12] = 0; } Y(clear_r12) |
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X(clear_r13) { cpu->cd.arm.r[13] = 0; } Y(clear_r13) |
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X(clear_r14) { cpu->cd.arm.r[14] = 0; } Y(clear_r14) |
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|
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|
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/* |
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* mov1_rX: Move #1 into a register. (Optimization hack.) |
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*/ |
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X(mov1_r0) { cpu->cd.arm.r[ 0] = 1; } Y(mov1_r0) |
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X(mov1_r1) { cpu->cd.arm.r[ 1] = 1; } Y(mov1_r1) |
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X(mov1_r2) { cpu->cd.arm.r[ 2] = 1; } Y(mov1_r2) |
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X(mov1_r3) { cpu->cd.arm.r[ 3] = 1; } Y(mov1_r3) |
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X(mov1_r4) { cpu->cd.arm.r[ 4] = 1; } Y(mov1_r4) |
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X(mov1_r5) { cpu->cd.arm.r[ 5] = 1; } Y(mov1_r5) |
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X(mov1_r6) { cpu->cd.arm.r[ 6] = 1; } Y(mov1_r6) |
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X(mov1_r7) { cpu->cd.arm.r[ 7] = 1; } Y(mov1_r7) |
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X(mov1_r8) { cpu->cd.arm.r[ 8] = 1; } Y(mov1_r8) |
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X(mov1_r9) { cpu->cd.arm.r[ 9] = 1; } Y(mov1_r9) |
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X(mov1_r10) { cpu->cd.arm.r[10] = 1; } Y(mov1_r10) |
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X(mov1_r11) { cpu->cd.arm.r[11] = 1; } Y(mov1_r11) |
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X(mov1_r12) { cpu->cd.arm.r[12] = 1; } Y(mov1_r12) |
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X(mov1_r13) { cpu->cd.arm.r[13] = 1; } Y(mov1_r13) |
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X(mov1_r14) { cpu->cd.arm.r[14] = 1; } Y(mov1_r14) |
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|
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/* |
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* add1_rX: Add #1 to a register. (Optimization hack.) |
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*/ |
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X(add1_r0) { cpu->cd.arm.r[ 0] ++; } Y(add1_r0) |
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X(add1_r1) { cpu->cd.arm.r[ 1] ++; } Y(add1_r1) |
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X(add1_r2) { cpu->cd.arm.r[ 2] ++; } Y(add1_r2) |
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X(add1_r3) { cpu->cd.arm.r[ 3] ++; } Y(add1_r3) |
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X(add1_r4) { cpu->cd.arm.r[ 4] ++; } Y(add1_r4) |
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X(add1_r5) { cpu->cd.arm.r[ 5] ++; } Y(add1_r5) |
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X(add1_r6) { cpu->cd.arm.r[ 6] ++; } Y(add1_r6) |
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X(add1_r7) { cpu->cd.arm.r[ 7] ++; } Y(add1_r7) |
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X(add1_r8) { cpu->cd.arm.r[ 8] ++; } Y(add1_r8) |
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X(add1_r9) { cpu->cd.arm.r[ 9] ++; } Y(add1_r9) |
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X(add1_r10) { cpu->cd.arm.r[10] ++; } Y(add1_r10) |
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X(add1_r11) { cpu->cd.arm.r[11] ++; } Y(add1_r11) |
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X(add1_r12) { cpu->cd.arm.r[12] ++; } Y(add1_r12) |
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X(add1_r13) { cpu->cd.arm.r[13] ++; } Y(add1_r13) |
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X(add1_r14) { cpu->cd.arm.r[14] ++; } Y(add1_r14) |
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