src/devices/dev_v3.c

/*
 *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *   
 *
 *  $Id: dev_v3.c,v 1.4 2006/02/18 17:55:25 debug Exp $
 *  
 *  V3 Semiconductor PCI controller.
 *
 *  See NetBSD's src/sys/arch/algor/pci/ for details.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>

#include "bus_pci.h"
#include "cpu.h"
#include "device.h"
#include "devices.h"
#include "machine.h"
#include "memory.h"
#include "misc.h"


DEVICE_ACCESS(v3_pci)
{
        uint64_t idata = 0, odata = 0;
        int bus, dev, func, reg;
        struct v3_data *d = extra;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN);

        /*  Decompose the tag:  */
        relative_addr &= 0xfffff;
        relative_addr |= ((d->lb_map0 & 0xfff0) << 16);
        bus = 0;
        for (dev=24; dev<32; dev++)
                if (relative_addr & (1 << dev))
                        break;
        dev -= 24;
        if (dev == 8) {
                fatal("[ v3_pci: NO DEVICE? ]\n");
                dev = 0;
        }
        func = (relative_addr >> 8) & 7;
        reg  = relative_addr & 0xfc;
        bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);

        /*  Pass semi-direct PCI accesses onto bus_pci:  */
        bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
            &odata : &idata, len, writeflag);

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len|MEM_PCI_LITTLE_ENDIAN, odata);

        return 1;
}


DEVICE_ACCESS(v3)
{
        struct v3_data *d = extra;
        uint64_t idata = 0, odata = 0;

        if (writeflag == MEM_WRITE)
                idata = memory_readmax64(cpu, data, len);

        switch (relative_addr) {

        case 0x06:      /*  PCI stat  */
                break;

        case 0x08:      /*  Revision  */
                odata = 4;
                break;

        case 0x18:      /*  PCI DMA base 1  */
                odata = 0x11000000;
                break;

        case 0x5e:      /*  LB MAP0  */
                if (writeflag == MEM_READ)
                        odata = d->lb_map0;
                else
                        d->lb_map0 = idata;
                break;

        case 0x62:      /*  PCI mem base 1  */
                odata = 0x1100;
                break;

        case 0x64:      /*  L2 BASE  */
                odata = 1;      /*  pci i/o enable  */
                break;

        case 0x66:      /*  Map 2  */
                odata = 0x1d00;
                break;

        default:if (writeflag == MEM_WRITE) {
                        fatal("[ v3: unimplemented write to "
                            "offset 0x%x: data=0x%x ]\n", (int)
                            relative_addr, (int)idata);
                } else {
                        fatal("[ v3: unimplemented read from "
                            "offset 0x%x ]\n", (int)relative_addr);
                }
        }

        if (writeflag == MEM_READ)
                memory_writemax64(cpu, data, len, odata);

        return 1;
}


struct v3_data *dev_v3_init(struct machine *machine, struct memory *mem)
{
        struct v3_data *d;

        d = malloc(sizeof(struct v3_data));
        if (d == NULL) {
                fprintf(stderr, "out of memory\n");
                exit(1);
        }
        memset(d, 0, sizeof(struct v3_data));

        /*  Register a PCI bus:  */
        d->pci_data = bus_pci_init(
            machine,
            0                   /*  pciirq: TODO  */,
            0x1d000000,         /*  pci device io offset  */
            0x11000000,         /*  pci device mem offset: TODO  */
            0x00000000,         /*  PCI portbase: TODO  */
            0x00000000,         /*  PCI membase: TODO  */
            0x00000000,         /*  PCI irqbase: TODO  */
            0x1d000000,         /*  ISA portbase  */
            0x10000000,         /*  ISA membase  */
            8);                 /*  ISA irqbase  */

        switch (machine->machine_type) {
        case MACHINE_ALGOR:
                bus_pci_add(machine, d->pci_data, mem, 0, 2, 0, "piix3_isa");
                bus_pci_add(machine, d->pci_data, mem, 0, 2, 1, "piix3_ide");
                break;
        default:fatal("!\n! WARNING: v3 for non-implemented machine"
                    " type %i\n!\n", machine->machine_type);
                exit(1);
        }

        /*  PCI configuration space:  */
        memory_device_register(mem, "v3_pci", 0x1ee00000, 0x100000,
            dev_v3_pci_access, d, DM_DEFAULT, NULL);

        /*  PCI controller:  */
        memory_device_register(mem, "v3", 0x1ef00000, 0x1000,
            dev_v3_access, d, DM_DEFAULT, NULL);

        return d;
}

1	/*
2	* Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: dev_v3.c,v 1.4 2006/02/18 17:55:25 debug Exp $
29	*
30	* V3 Semiconductor PCI controller.
31	*
32	* See NetBSD's src/sys/arch/algor/pci/ for details.
33	*/
34
35	#include <stdio.h>
36	#include <stdlib.h>
37	#include <string.h>
38
39	#include "bus_pci.h"
40	#include "cpu.h"
41	#include "device.h"
42	#include "devices.h"
43	#include "machine.h"
44	#include "memory.h"
45	#include "misc.h"
46
47
48	DEVICE_ACCESS(v3_pci)
49	{
50	uint64_t idata = 0, odata = 0;
51	int bus, dev, func, reg;
52	struct v3_data *d = extra;
53
54	if (writeflag == MEM_WRITE)
55	idata = memory_readmax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN);
56
57	/* Decompose the tag: */
58	relative_addr &= 0xfffff;
59	relative_addr \|= ((d->lb_map0 & 0xfff0) << 16);
60	bus = 0;
61	for (dev=24; dev<32; dev++)
62	if (relative_addr & (1 << dev))
63	break;
64	dev -= 24;
65	if (dev == 8) {
66	fatal("[ v3_pci: NO DEVICE? ]\n");
67	dev = 0;
68	}
69	func = (relative_addr >> 8) & 7;
70	reg = relative_addr & 0xfc;
71	bus_pci_setaddr(cpu, d->pci_data, bus, dev, func, reg);
72
73	/* Pass semi-direct PCI accesses onto bus_pci: */
74	bus_pci_data_access(cpu, d->pci_data, writeflag == MEM_READ?
75	&odata : &idata, len, writeflag);
76
77	if (writeflag == MEM_READ)
78	memory_writemax64(cpu, data, len\|MEM_PCI_LITTLE_ENDIAN, odata);
79
80	return 1;
81	}
82
83
84	DEVICE_ACCESS(v3)
85	{
86	struct v3_data *d = extra;
87	uint64_t idata = 0, odata = 0;
88
89	if (writeflag == MEM_WRITE)
90	idata = memory_readmax64(cpu, data, len);
91
92	switch (relative_addr) {
93
94	case 0x06: /* PCI stat */
95	break;
96
97	case 0x08: /* Revision */
98	odata = 4;
99	break;
100
101	case 0x18: /* PCI DMA base 1 */
102	odata = 0x11000000;
103	break;
104
105	case 0x5e: /* LB MAP0 */
106	if (writeflag == MEM_READ)
107	odata = d->lb_map0;
108	else
109	d->lb_map0 = idata;
110	break;
111
112	case 0x62: /* PCI mem base 1 */
113	odata = 0x1100;
114	break;
115
116	case 0x64: /* L2 BASE */
117	odata = 1; /* pci i/o enable */
118	break;
119
120	case 0x66: /* Map 2 */
121	odata = 0x1d00;
122	break;
123
124	default:if (writeflag == MEM_WRITE) {
125	fatal("[ v3: unimplemented write to "
126	"offset 0x%x: data=0x%x ]\n", (int)
127	relative_addr, (int)idata);
128	} else {
129	fatal("[ v3: unimplemented read from "
130	"offset 0x%x ]\n", (int)relative_addr);
131	}
132	}
133
134	if (writeflag == MEM_READ)
135	memory_writemax64(cpu, data, len, odata);
136
137	return 1;
138	}
139
140
141	struct v3_data dev_v3_init(struct machine machine, struct memory *mem)
142	{
143	struct v3_data *d;
144
145	d = malloc(sizeof(struct v3_data));
146	if (d == NULL) {
147	fprintf(stderr, "out of memory\n");
148	exit(1);
149	}
150	memset(d, 0, sizeof(struct v3_data));
151
152	/* Register a PCI bus: */
153	d->pci_data = bus_pci_init(
154	machine,
155	0 /* pciirq: TODO */,
156	0x1d000000, /* pci device io offset */
157	0x11000000, /* pci device mem offset: TODO */
158	0x00000000, /* PCI portbase: TODO */
159	0x00000000, /* PCI membase: TODO */
160	0x00000000, /* PCI irqbase: TODO */
161	0x1d000000, /* ISA portbase */
162	0x10000000, /* ISA membase */
163	8); /* ISA irqbase */
164
165	switch (machine->machine_type) {
166	case MACHINE_ALGOR:
167	bus_pci_add(machine, d->pci_data, mem, 0, 2, 0, "piix3_isa");
168	bus_pci_add(machine, d->pci_data, mem, 0, 2, 1, "piix3_ide");
169	break;
170	default:fatal("!\n! WARNING: v3 for non-implemented machine"
171	" type %i\n!\n", machine->machine_type);
172	exit(1);
173	}
174
175	/* PCI configuration space: */
176	memory_device_register(mem, "v3_pci", 0x1ee00000, 0x100000,
177	dev_v3_pci_access, d, DM_DEFAULT, NULL);
178
179	/* PCI controller: */
180	memory_device_register(mem, "v3", 0x1ef00000, 0x1000,
181	dev_v3_access, d, DM_DEFAULT, NULL);
182
183	return d;
184	}
185