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/* |
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* Copyright (C) 2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_transputer_instr.c,v 1.6 2006/07/23 19:36:14 debug Exp $ |
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* |
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* INMOS transputer instructions. |
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* |
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* Individual functions should keep track of cpu->n_translated_instrs. |
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* (n_translated_instrs is automatically increased by 1 for each function |
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* call. If no instruction was executed, then it should be decreased. If, say, |
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* 4 instructions were combined into one function and executed, then it should |
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* be increased by 3.) |
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* |
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* NOTE: The PC does not need to be synched before e.g. memory_rw(), because |
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* there is no MMU in the Transputer, and hence there can not be any |
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* exceptions on memory accesses. |
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*/ |
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|
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|
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/*****************************************************************************/ |
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|
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|
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/* |
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* j: Relative jump |
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*/ |
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X(j) |
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{ |
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/* Synchronize the PC and then add the operand + 1: */ |
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int low_pc = ((size_t)ic - (size_t)cpu->cd.transputer.cur_ic_page) |
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/ sizeof(struct transputer_instr_call); |
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cpu->pc &= ~(TRANSPUTER_IC_ENTRIES_PER_PAGE-1); |
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cpu->pc += low_pc + ic->arg[0] + 1 + cpu->cd.transputer.oreg; |
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cpu->cd.transputer.oreg = 0; |
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quick_pc_to_pointers(cpu); |
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} |
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|
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|
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/* |
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* ldlp: Load local pointer |
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*/ |
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X(ldlp) |
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{ |
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cpu->cd.transputer.c = cpu->cd.transputer.b; |
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cpu->cd.transputer.b = cpu->cd.transputer.a; |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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cpu->cd.transputer.a = cpu->cd.transputer.oreg * sizeof(uint32_t) + |
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cpu->cd.transputer.wptr; |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* pfix: Prefix |
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* |
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* arg[0] = nibble |
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*/ |
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X(pfix) |
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{ |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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cpu->cd.transputer.oreg <<= 4; |
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} |
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|
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|
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/* |
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* ldnl: Load non-local |
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*/ |
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X(ldnl) |
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{ |
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uint32_t addr, w32; |
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uint8_t word[sizeof(uint32_t)]; |
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unsigned char *page; |
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|
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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addr = cpu->cd.transputer.oreg * sizeof(uint32_t) + |
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cpu->cd.transputer.a; |
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|
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page = cpu->cd.transputer.host_load[TRANSPUTER_ADDR_TO_PAGENR(addr)]; |
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if (page == NULL) { |
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cpu->memory_rw(cpu, cpu->mem, addr, word, sizeof(word), |
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MEM_READ, CACHE_DATA); |
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w32 = *(uint32_t *) &word[0]; |
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} else { |
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w32 = *(uint32_t *) &page[TRANSPUTER_PC_TO_IC_ENTRY(addr)]; |
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} |
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|
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cpu->cd.transputer.a = LE32_TO_HOST(w32); |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* ldc: Load constant |
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*/ |
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X(ldc) |
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{ |
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cpu->cd.transputer.c = cpu->cd.transputer.b; |
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cpu->cd.transputer.b = cpu->cd.transputer.a; |
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cpu->cd.transputer.a = cpu->cd.transputer.oreg | ic->arg[0]; |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* ldnlp: Load non-local pointer |
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*/ |
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X(ldnlp) |
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{ |
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cpu->cd.transputer.a += (cpu->cd.transputer.oreg | ic->arg[0]) |
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* sizeof(uint32_t); |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* nfix: Negative prefix |
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*/ |
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X(nfix) |
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{ |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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cpu->cd.transputer.oreg = (~cpu->cd.transputer.oreg) << 4; |
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} |
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|
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|
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/* |
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* ldl: Load local |
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*/ |
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X(ldl) |
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{ |
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uint32_t addr; |
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uint8_t word[sizeof(uint32_t)]; |
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uint32_t w32; |
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unsigned char *page; |
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|
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cpu->cd.transputer.c = cpu->cd.transputer.b; |
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cpu->cd.transputer.b = cpu->cd.transputer.a; |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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addr = cpu->cd.transputer.oreg * sizeof(uint32_t) + |
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cpu->cd.transputer.wptr; |
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|
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page = cpu->cd.transputer.host_load[TRANSPUTER_ADDR_TO_PAGENR(addr)]; |
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if (page == NULL) { |
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cpu->memory_rw(cpu, cpu->mem, addr, word, sizeof(word), |
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MEM_READ, CACHE_DATA); |
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w32 = *(uint32_t *) &word[0]; |
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printf("A w32 = %08"PRIx32"\n", w32); |
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} else { |
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w32 = *(uint32_t *) &page[TRANSPUTER_PC_TO_IC_ENTRY(addr)]; |
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printf("B w32 = %08"PRIx32"\n", w32); |
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} |
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|
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cpu->cd.transputer.a = LE32_TO_HOST(w32); |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* ajw: Adjust workspace |
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*/ |
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X(ajw) |
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{ |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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cpu->cd.transputer.wptr += (cpu->cd.transputer.oreg * sizeof(uint32_t)); |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* eqc: Equal to constant |
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*/ |
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X(eqc) |
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{ |
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cpu->cd.transputer.a = (cpu->cd.transputer.a == |
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(cpu->cd.transputer.oreg | ic->arg[0])); |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* stl: Store local |
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*/ |
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X(stl) |
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{ |
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uint32_t addr, w32; |
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unsigned char *page; |
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|
| 210 |
w32 = LE32_TO_HOST(cpu->cd.transputer.a); |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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addr = cpu->cd.transputer.oreg * sizeof(uint32_t) + |
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cpu->cd.transputer.wptr; |
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|
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page = cpu->cd.transputer.host_store[TRANSPUTER_ADDR_TO_PAGENR(addr)]; |
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if (page == NULL) { |
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cpu->memory_rw(cpu, cpu->mem, addr, (void *)&w32, sizeof(w32), |
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MEM_WRITE, CACHE_DATA); |
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} else { |
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*((uint32_t *) &page[TRANSPUTER_PC_TO_IC_ENTRY(addr)]) = w32; |
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} |
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|
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cpu->cd.transputer.a = cpu->cd.transputer.b; |
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cpu->cd.transputer.b = cpu->cd.transputer.c; |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* stnl: Store non-local |
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*/ |
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X(stnl) |
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{ |
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uint32_t addr, w32; |
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unsigned char *page; |
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|
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w32 = LE32_TO_HOST(cpu->cd.transputer.b); |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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addr = cpu->cd.transputer.oreg * sizeof(uint32_t) + |
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cpu->cd.transputer.a; |
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|
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page = cpu->cd.transputer.host_store[TRANSPUTER_ADDR_TO_PAGENR(addr)]; |
| 243 |
if (page == NULL) { |
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cpu->memory_rw(cpu, cpu->mem, addr, (void *)&w32, sizeof(w32), |
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MEM_WRITE, CACHE_DATA); |
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} else { |
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*((uint32_t *) &page[TRANSPUTER_PC_TO_IC_ENTRY(addr)]) = w32; |
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} |
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|
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cpu->cd.transputer.a = cpu->cd.transputer.c; |
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cpu->cd.transputer.oreg = 0; |
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} |
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|
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|
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/* |
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* opr: Operate |
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* |
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* TODO/NOTE: This doesn't work too well with the way dyntrans is designed |
| 259 |
* to work. Maybe it should be rewritten some day. But how? |
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* Right now it works almost 100% like an old-style interpretation |
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* function. |
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*/ |
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X(opr) |
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{ |
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cpu->cd.transputer.oreg |= ic->arg[0]; |
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|
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switch (cpu->cd.transputer.oreg) { |
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|
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case T_OPC_F_REV: |
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{ |
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uint32_t tmp = cpu->cd.transputer.b; |
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cpu->cd.transputer.b = cpu->cd.transputer.a; |
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cpu->cd.transputer.a = tmp; |
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} |
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break; |
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|
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case T_OPC_F_ADD: |
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{ |
| 279 |
uint32_t old_a = cpu->cd.transputer.a; |
| 280 |
cpu->cd.transputer.a = cpu->cd.transputer.b + old_a; |
| 281 |
if ((cpu->cd.transputer.a & 0x80000000) != |
| 282 |
(cpu->cd.transputer.b & old_a & 0x80000000)) |
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cpu->cd.transputer.error = 1; |
| 284 |
cpu->cd.transputer.b = cpu->cd.transputer.c; |
| 285 |
} |
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break; |
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|
| 288 |
case T_OPC_F_SUB: |
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{ |
| 290 |
uint32_t old_a = cpu->cd.transputer.a; |
| 291 |
cpu->cd.transputer.a = cpu->cd.transputer.b - old_a; |
| 292 |
if ((cpu->cd.transputer.a & 0x80000000) != |
| 293 |
(cpu->cd.transputer.b & old_a & 0x80000000)) |
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cpu->cd.transputer.error = 1; |
| 295 |
cpu->cd.transputer.b = cpu->cd.transputer.c; |
| 296 |
} |
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break; |
| 298 |
|
| 299 |
case T_OPC_F_LDPI: |
| 300 |
/* Load pointer to (next) instruction */ |
| 301 |
{ |
| 302 |
int low_pc = ((size_t)ic - |
| 303 |
(size_t)cpu->cd.transputer.cur_ic_page) |
| 304 |
/ sizeof(struct transputer_instr_call); |
| 305 |
cpu->pc &= ~(TRANSPUTER_IC_ENTRIES_PER_PAGE-1); |
| 306 |
cpu->pc += low_pc; |
| 307 |
cpu->cd.transputer.a += cpu->pc + 1; |
| 308 |
} |
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break; |
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|
| 311 |
case T_OPC_F_STHF: |
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cpu->cd.transputer.fptrreg0 = cpu->cd.transputer.a; |
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cpu->cd.transputer.a = cpu->cd.transputer.b; |
| 314 |
cpu->cd.transputer.b = cpu->cd.transputer.c; |
| 315 |
break; |
| 316 |
|
| 317 |
case T_OPC_F_STLF: |
| 318 |
cpu->cd.transputer.fptrreg1 = cpu->cd.transputer.a; |
| 319 |
cpu->cd.transputer.a = cpu->cd.transputer.b; |
| 320 |
cpu->cd.transputer.b = cpu->cd.transputer.c; |
| 321 |
break; |
| 322 |
|
| 323 |
case T_OPC_F_BCNT: |
| 324 |
cpu->cd.transputer.a <<= 2; |
| 325 |
break; |
| 326 |
|
| 327 |
case T_OPC_F_GAJW: |
| 328 |
{ |
| 329 |
uint32_t old_wptr = cpu->cd.transputer.wptr; |
| 330 |
cpu->cd.transputer.wptr = cpu->cd.transputer.a & ~3; |
| 331 |
cpu->cd.transputer.a = old_wptr; |
| 332 |
} |
| 333 |
break; |
| 334 |
|
| 335 |
case T_OPC_F_WCNT: |
| 336 |
cpu->cd.transputer.c = cpu->cd.transputer.b; |
| 337 |
cpu->cd.transputer.b = cpu->cd.transputer.a & 3; |
| 338 |
cpu->cd.transputer.a >>= 2; |
| 339 |
break; |
| 340 |
|
| 341 |
case T_OPC_F_MINT: |
| 342 |
cpu->cd.transputer.c = cpu->cd.transputer.b; |
| 343 |
cpu->cd.transputer.b = cpu->cd.transputer.a; |
| 344 |
cpu->cd.transputer.a = 0x80000000; |
| 345 |
break; |
| 346 |
|
| 347 |
case T_OPC_F_MOVE: |
| 348 |
/* TODO: This can be optimized a lot by using the host's |
| 349 |
memmove(). The only important thing to consider is |
| 350 |
if src or dst crosses a host memblock boundary. */ |
| 351 |
{ |
| 352 |
uint32_t i, src = cpu->cd.transputer.c, |
| 353 |
dst = cpu->cd.transputer.b; |
| 354 |
uint8_t byte; |
| 355 |
for (i=1; i<=cpu->cd.transputer.a; i++) { |
| 356 |
cpu->memory_rw(cpu, cpu->mem, src ++, &byte, |
| 357 |
1, MEM_READ, CACHE_DATA); |
| 358 |
cpu->memory_rw(cpu, cpu->mem, dst ++, &byte, |
| 359 |
1, MEM_WRITE, CACHE_DATA); |
| 360 |
} |
| 361 |
} |
| 362 |
break; |
| 363 |
|
| 364 |
default:fatal("UNIMPLEMENTED opr oreg 0x%"PRIx32"\n", |
| 365 |
cpu->cd.transputer.oreg); |
| 366 |
exit(1); |
| 367 |
} |
| 368 |
|
| 369 |
cpu->cd.transputer.oreg = 0; |
| 370 |
} |
| 371 |
|
| 372 |
|
| 373 |
/*****************************************************************************/ |
| 374 |
|
| 375 |
|
| 376 |
X(end_of_page) |
| 377 |
{ |
| 378 |
/* Update the PC: (offset 0, but on the next page) */ |
| 379 |
cpu->pc &= ~((TRANSPUTER_IC_ENTRIES_PER_PAGE-1) << 1); |
| 380 |
cpu->pc += (TRANSPUTER_IC_ENTRIES_PER_PAGE << 1); |
| 381 |
|
| 382 |
/* Find the new physical page and update the translation pointers: */ |
| 383 |
transputer_pc_to_pointers(cpu); |
| 384 |
|
| 385 |
/* end_of_page doesn't count as an executed instruction: */ |
| 386 |
cpu->n_translated_instrs --; |
| 387 |
} |
| 388 |
|
| 389 |
|
| 390 |
/*****************************************************************************/ |
| 391 |
|
| 392 |
|
| 393 |
/* |
| 394 |
* transputer_instr_to_be_translated(): |
| 395 |
* |
| 396 |
* Translate an instruction word into an transputer_instr_call. ic is filled in with |
| 397 |
* valid data for the translated instruction, or a "nothing" instruction if |
| 398 |
* there was a translation failure. The newly translated instruction is then |
| 399 |
* executed. |
| 400 |
*/ |
| 401 |
X(to_be_translated) |
| 402 |
{ |
| 403 |
uint32_t addr, low_pc; |
| 404 |
unsigned char *page; |
| 405 |
unsigned char ib[1]; |
| 406 |
/* void (*samepage_function)(struct cpu *, |
| 407 |
struct transputer_instr_call *);*/ |
| 408 |
|
| 409 |
/* Figure out the (virtual) address of the instruction: */ |
| 410 |
low_pc = ((size_t)ic - (size_t)cpu->cd.transputer.cur_ic_page) |
| 411 |
/ sizeof(struct transputer_instr_call); |
| 412 |
addr = cpu->pc & ~((TRANSPUTER_IC_ENTRIES_PER_PAGE-1) << |
| 413 |
TRANSPUTER_INSTR_ALIGNMENT_SHIFT); |
| 414 |
addr += (low_pc << TRANSPUTER_INSTR_ALIGNMENT_SHIFT); |
| 415 |
cpu->pc = addr; |
| 416 |
addr &= ~((1 << TRANSPUTER_INSTR_ALIGNMENT_SHIFT) - 1); |
| 417 |
|
| 418 |
/* Read the instruction word from memory: */ |
| 419 |
page = cpu->cd.transputer.host_load[addr >> 12]; |
| 420 |
|
| 421 |
if (page != NULL) { |
| 422 |
/* fatal("TRANSLATION HIT!\n"); */ |
| 423 |
memcpy(ib, page + (addr & 0xfff), sizeof(ib)); |
| 424 |
} else { |
| 425 |
/* fatal("TRANSLATION MISS!\n"); */ |
| 426 |
if (!cpu->memory_rw(cpu, cpu->mem, addr, ib, |
| 427 |
sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) { |
| 428 |
fatal("to_be_translated(): " |
| 429 |
"read failed: TODO\n"); |
| 430 |
goto bad; |
| 431 |
} |
| 432 |
} |
| 433 |
|
| 434 |
|
| 435 |
#define DYNTRANS_TO_BE_TRANSLATED_HEAD |
| 436 |
#include "cpu_dyntrans.c" |
| 437 |
#undef DYNTRANS_TO_BE_TRANSLATED_HEAD |
| 438 |
|
| 439 |
|
| 440 |
/* |
| 441 |
* Translate the instruction: |
| 442 |
* -------------------------- |
| 443 |
* |
| 444 |
* Most instructions take the operand as arg[0], so we set it |
| 445 |
* here by default: |
| 446 |
*/ |
| 447 |
ic->arg[0] = ib[0] & 0xf; |
| 448 |
|
| 449 |
switch (ib[0] >> 4) { |
| 450 |
|
| 451 |
case T_OPC_J: |
| 452 |
/* relative jump */ |
| 453 |
ic->f = instr(j); |
| 454 |
/* TODO: Samepage jump! */ |
| 455 |
|
| 456 |
if (cpu->cd.transputer.cpu_type.features & T_DEBUG |
| 457 |
&& (ib[0] & 0xf) == 0) { |
| 458 |
/* |
| 459 |
* From Wikipedia: ... "and, later, the T225. This |
| 460 |
* added debugging breakpoint support (by extending |
| 461 |
* the instruction J 0)" |
| 462 |
*/ |
| 463 |
fatal("TODO: Transputer Debugger support!\n"); |
| 464 |
goto bad; |
| 465 |
} |
| 466 |
break; |
| 467 |
|
| 468 |
case T_OPC_LDLP: |
| 469 |
/* load local pointer */ |
| 470 |
ic->f = instr(ldlp); |
| 471 |
break; |
| 472 |
|
| 473 |
case T_OPC_PFIX: |
| 474 |
/* prefix */ |
| 475 |
ic->f = instr(pfix); |
| 476 |
break; |
| 477 |
|
| 478 |
case T_OPC_LDNL: |
| 479 |
/* load non-local */ |
| 480 |
ic->f = instr(ldnl); |
| 481 |
break; |
| 482 |
|
| 483 |
case T_OPC_LDC: |
| 484 |
/* load constant */ |
| 485 |
ic->f = instr(ldc); |
| 486 |
break; |
| 487 |
|
| 488 |
case T_OPC_LDNLP: |
| 489 |
/* load non-local pointer */ |
| 490 |
ic->f = instr(ldnlp); |
| 491 |
break; |
| 492 |
|
| 493 |
case T_OPC_NFIX: |
| 494 |
/* negative prefix */ |
| 495 |
ic->f = instr(nfix); |
| 496 |
break; |
| 497 |
|
| 498 |
case T_OPC_LDL: |
| 499 |
/* load local */ |
| 500 |
ic->f = instr(ldl); |
| 501 |
break; |
| 502 |
|
| 503 |
case T_OPC_AJW: |
| 504 |
/* adjust workspace */ |
| 505 |
ic->f = instr(ajw); |
| 506 |
break; |
| 507 |
|
| 508 |
case T_OPC_EQC: |
| 509 |
/* equal to constant */ |
| 510 |
ic->f = instr(eqc); |
| 511 |
break; |
| 512 |
|
| 513 |
case T_OPC_STL: |
| 514 |
/* store local */ |
| 515 |
ic->f = instr(stl); |
| 516 |
break; |
| 517 |
|
| 518 |
case T_OPC_STNL: |
| 519 |
/* store non-local */ |
| 520 |
ic->f = instr(stnl); |
| 521 |
break; |
| 522 |
|
| 523 |
case T_OPC_OPR: |
| 524 |
/* operate */ |
| 525 |
ic->f = instr(opr); |
| 526 |
break; |
| 527 |
|
| 528 |
default:fatal("UNIMPLEMENTED opcode 0x%02x\n", ib[0]); |
| 529 |
goto bad; |
| 530 |
} |
| 531 |
|
| 532 |
|
| 533 |
#define DYNTRANS_TO_BE_TRANSLATED_TAIL |
| 534 |
#include "cpu_dyntrans.c" |
| 535 |
#undef DYNTRANS_TO_BE_TRANSLATED_TAIL |
| 536 |
} |
| 537 |
|
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