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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_ppc_instr_loadstore.c,v 1.9 2006/04/02 10:21:08 debug Exp $ |
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* |
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* POWER/PowerPC load/store instructions. |
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* |
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* |
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* Load/store instructions have the following arguments: |
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* |
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* arg[0] = pointer to the register to load to or store from |
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* arg[1] = pointer to the base register |
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* |
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* arg[2] = offset (as an int32_t) |
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* (or, for Indexed load/stores: pointer to index register) |
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*/ |
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|
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|
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#ifndef LS_IGNOREOFS |
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void LS_GENERIC_N(struct cpu *cpu, struct ppc_instr_call *ic) |
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{ |
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#ifdef MODE32 |
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uint32_t addr = |
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#else |
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uint64_t addr = |
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#endif |
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reg(ic->arg[1]) + |
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#ifdef LS_INDEXED |
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reg(ic->arg[2]); |
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#else |
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(int32_t)ic->arg[2]; |
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#endif |
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unsigned char data[LS_SIZE]; |
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|
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/* Synchronize the PC: */ |
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int low_pc = ((size_t)ic - (size_t)cpu->cd.ppc.cur_ic_page) |
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/ sizeof(struct ppc_instr_call); |
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cpu->pc &= ~((PPC_IC_ENTRIES_PER_PAGE-1) << PPC_INSTR_ALIGNMENT_SHIFT); |
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cpu->pc += (low_pc << PPC_INSTR_ALIGNMENT_SHIFT); |
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|
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#ifndef LS_B |
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if ((addr & 0xfff) + LS_SIZE-1 > 0xfff) { |
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fatal("PPC LOAD/STORE misalignment across page boundary: TODO" |
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" (addr=0x%08x, LS_SIZE=%i)\n", (int)addr, LS_SIZE); |
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exit(1); |
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} |
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#endif |
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|
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#ifdef LS_LOAD |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_READ, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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#ifdef LS_B |
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reg(ic->arg[0]) = |
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#ifndef LS_ZERO |
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(int8_t) |
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#endif |
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data[0]; |
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#endif |
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#ifdef LS_H |
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reg(ic->arg[0]) = |
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#ifdef LS_BYTEREVERSE |
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((data[1] << 8) + data[0]); |
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#else |
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#ifndef LS_ZERO |
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(int16_t) |
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#endif |
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((data[0] << 8) + data[1]); |
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#endif /* !BYTEREVERSE */ |
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#endif |
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#ifdef LS_W |
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reg(ic->arg[0]) = |
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#ifdef LS_BYTEREVERSE |
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((data[3] << 24) + (data[2] << 16) + |
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(data[1] << 8) + data[0]); |
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#else /* !LS_BYTEREVERSE */ |
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#ifndef LS_ZERO |
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(int32_t) |
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#else |
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(uint32_t) |
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#endif |
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((data[0] << 24) + (data[1] << 16) + |
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(data[2] << 8) + data[3]); |
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#endif /* !LS_BYTEREVERSE */ |
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#endif |
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#ifdef LS_D |
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(*(uint64_t *)(ic->arg[0])) = |
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((uint64_t)data[0] << 56) + ((uint64_t)data[1] << 48) + |
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((uint64_t)data[2] << 40) + ((uint64_t)data[3] << 32) + |
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((uint64_t)data[4] << 24) + (data[5] << 16) + |
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(data[6] << 8) + data[7]; |
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#endif |
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|
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#else /* store: */ |
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|
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#ifdef LS_B |
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data[0] = reg(ic->arg[0]); |
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#endif |
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#ifdef LS_H |
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#ifdef LS_BYTEREVERSE |
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data[0] = reg(ic->arg[0]); |
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data[1] = reg(ic->arg[0]) >> 8; |
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#else |
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data[0] = reg(ic->arg[0]) >> 8; |
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data[1] = reg(ic->arg[0]); |
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#endif |
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#endif |
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#ifdef LS_W |
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#ifdef LS_BYTEREVERSE |
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data[0] = reg(ic->arg[0]); |
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data[1] = reg(ic->arg[0]) >> 8; |
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data[2] = reg(ic->arg[0]) >> 16; |
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data[3] = reg(ic->arg[0]) >> 24; |
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#else |
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data[0] = reg(ic->arg[0]) >> 24; |
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data[1] = reg(ic->arg[0]) >> 16; |
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data[2] = reg(ic->arg[0]) >> 8; |
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data[3] = reg(ic->arg[0]); |
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#endif /* !LS_BYTEREVERSE */ |
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#endif |
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#ifdef LS_D |
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{ uint64_t x = *(uint64_t *)(ic->arg[0]); |
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data[0] = x >> 56; |
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data[1] = x >> 48; |
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data[2] = x >> 40; |
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data[3] = x >> 32; |
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data[4] = x >> 24; |
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data[5] = x >> 16; |
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data[6] = x >> 8; |
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data[7] = x; } |
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#endif |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_WRITE, CACHE_DATA)) { |
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/* Exception. */ |
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return; |
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} |
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#endif |
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|
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#ifdef LS_UPDATE |
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reg(ic->arg[1]) = addr; |
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#endif |
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} |
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#endif |
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|
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|
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void LS_N(struct cpu *cpu, struct ppc_instr_call *ic) |
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{ |
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#ifdef MODE32 |
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uint32_t addr = |
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#else |
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uint64_t addr = |
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#endif |
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reg(ic->arg[1]) |
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#ifdef LS_INDEXED |
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+ reg(ic->arg[2]) |
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#else |
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#ifndef LS_IGNOREOFS |
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+ (int32_t)ic->arg[2] |
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#endif |
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#endif |
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; |
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|
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unsigned char *page = cpu->cd.ppc. |
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#ifdef LS_LOAD |
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host_load |
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#else |
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host_store |
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#endif |
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[addr >> 12]; |
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#ifdef LS_UPDATE |
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uint32_t new_addr = addr; |
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#endif |
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|
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#ifndef LS_B |
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if (addr & (LS_SIZE-1)) { |
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LS_GENERIC_N(cpu, ic); |
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return; |
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} |
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#endif |
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|
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|
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#ifndef MODE32 |
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/*******************************************/ |
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if (!cpu->is_32bit) { |
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LS_GENERIC_N(cpu, ic); |
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return; |
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} |
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/*******************************************/ |
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#endif |
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|
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|
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if (page == NULL) { |
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LS_GENERIC_N(cpu, ic); |
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return; |
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} else { |
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addr &= 4095; |
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#ifdef LS_LOAD |
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/* Load: */ |
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#ifdef LS_B |
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reg(ic->arg[0]) = |
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#ifndef LS_ZERO |
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(int8_t) |
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#endif |
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page[addr]; |
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#endif /* LS_B */ |
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#ifdef LS_H |
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reg(ic->arg[0]) = |
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#ifdef LS_BYTEREVERSE |
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((page[addr+1] << 8) + page[addr]); |
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#else |
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#ifndef LS_ZERO |
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(int16_t) |
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#endif |
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((page[addr] << 8) + page[addr+1]); |
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#endif /* !BYTEREVERSE */ |
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#endif /* LS_H */ |
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#ifdef LS_W |
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reg(ic->arg[0]) = |
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#ifdef LS_BYTEREVERSE |
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((page[addr+3] << 24) + (page[addr+2] << 16) + |
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(page[addr+1] << 8) + page[addr]); |
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#else /* !LS_BYTEREVERSE */ |
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#ifndef LS_ZERO |
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(int32_t) |
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#else |
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(uint32_t) |
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#endif |
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((page[addr] << 24) + (page[addr+1] << 16) + |
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(page[addr+2] << 8) + page[addr+3]); |
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#endif /* !LS_BYTEREVERSE */ |
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#endif /* LS_W */ |
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#ifdef LS_D |
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(*(uint64_t *)(ic->arg[0])) = |
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((uint64_t)page[addr+0] << 56) + |
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((uint64_t)page[addr+1] << 48) + |
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((uint64_t)page[addr+2] << 40) + |
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((uint64_t)page[addr+3] << 32) + |
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((uint64_t)page[addr+4] << 24) + (page[addr+5] << 16) + |
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(page[addr+6] << 8) + page[addr+7]; |
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#endif /* LS_D */ |
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|
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#else /* !LS_LOAD */ |
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|
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/* Store: */ |
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#ifdef LS_B |
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page[addr] = reg(ic->arg[0]); |
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#endif |
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#ifdef LS_H |
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#ifdef LS_BYTEREVERSE |
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page[addr] = reg(ic->arg[0]); |
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page[addr+1] = reg(ic->arg[0]) >> 8; |
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#else |
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page[addr] = reg(ic->arg[0]) >> 8; |
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page[addr+1] = reg(ic->arg[0]); |
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#endif /* !BYTEREVERSE */ |
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#endif |
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#ifdef LS_W |
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#ifdef LS_BYTEREVERSE |
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page[addr] = reg(ic->arg[0]); |
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page[addr+1] = reg(ic->arg[0]) >> 8; |
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page[addr+2] = reg(ic->arg[0]) >> 16; |
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page[addr+3] = reg(ic->arg[0]) >> 24; |
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#else |
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page[addr] = reg(ic->arg[0]) >> 24; |
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page[addr+1] = reg(ic->arg[0]) >> 16; |
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page[addr+2] = reg(ic->arg[0]) >> 8; |
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page[addr+3] = reg(ic->arg[0]); |
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#endif /* !LS_BYTEREVERSE */ |
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#endif |
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#ifdef LS_D |
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{ uint64_t x = *(uint64_t *)(ic->arg[0]); |
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page[addr] = x >> 56; |
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page[addr+1] = x >> 48; |
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page[addr+2] = x >> 40; |
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page[addr+3] = x >> 32; |
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page[addr+4] = x >> 24; |
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page[addr+5] = x >> 16; |
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page[addr+6] = x >> 8; |
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page[addr+7] = x; } |
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#endif |
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#endif /* !LS_LOAD */ |
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} |
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|
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#ifdef LS_UPDATE |
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reg(ic->arg[1]) = new_addr; |
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#endif |
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} |
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