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/* |
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* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_alpha_instr_loadstore.c,v 1.5 2006/06/30 20:22:53 debug Exp $ |
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* |
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* Alpha load/store instructions. (Included from cpu_alpha_instr_inc.c.) |
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* |
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* |
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* Load/store instructions have the following arguments: |
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* |
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* arg[0] = pointer to the register to load to or store from (uint64_t) |
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* arg[1] = pointer to the base register (uint64_t) |
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* arg[2] = offset (as an int32_t) |
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* |
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* NOTE: |
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* Alpha byte and word loads (8- and 16-bit) are unsigned, while |
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* 32-bit long words are sign-extended up to 64 bits during a load! |
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*/ |
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|
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|
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#ifndef LS_IGNORE_OFFSET |
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static void LS_GENERIC_N(struct cpu *cpu, struct alpha_instr_call *ic) |
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{ |
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#ifdef LS_B |
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unsigned char data[1]; |
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#endif |
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#ifdef LS_W |
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unsigned char data[2]; |
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#endif |
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#ifdef LS_L |
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unsigned char data[4]; |
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#endif |
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#ifdef LS_Q |
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unsigned char data[8]; |
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#endif |
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uint64_t addr = *((uint64_t *)ic->arg[1]); |
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uint64_t data_x; |
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|
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addr += (int32_t)ic->arg[2]; |
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#ifdef LS_UNALIGNED |
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addr &= ~7; |
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#endif |
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|
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#ifdef LS_LOAD |
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/* Load: */ |
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_READ, CACHE_DATA)) { |
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fatal("store failed: TODO\n"); |
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exit(1); |
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} |
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|
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data_x = data[0]; |
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#ifndef LS_B |
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data_x += (data[1] << 8); |
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#ifndef LS_W |
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data_x += (data[2] << 16); |
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data_x += ((uint64_t)data[3] << 24); |
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#ifdef LS_L |
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data_x = (int64_t)(int32_t)data_x; |
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#endif |
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#ifndef LS_L |
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data_x += ((uint64_t)data[4] << 32); |
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data_x += ((uint64_t)data[5] << 40); |
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data_x += ((uint64_t)data[6] << 48); |
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data_x += ((uint64_t)data[7] << 56); |
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#endif |
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#endif |
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#endif |
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*((uint64_t *)ic->arg[0]) = data_x; |
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#else |
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/* Store: */ |
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data_x = *((uint64_t *)ic->arg[0]); |
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data[0] = data_x; |
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#ifndef LS_B |
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data[1] = data_x >> 8; |
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#ifndef LS_W |
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data[2] = data_x >> 16; |
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data[3] = data_x >> 24; |
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#ifndef LS_L |
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data[4] = data_x >> 32; |
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data[5] = data_x >> 40; |
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data[6] = data_x >> 48; |
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data[7] = data_x >> 56; |
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#endif |
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#endif |
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#endif |
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|
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if (!cpu->memory_rw(cpu, cpu->mem, addr, data, sizeof(data), |
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MEM_WRITE, CACHE_DATA)) { |
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fatal("store failed: TODO\n"); |
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exit(1); |
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} |
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|
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#ifdef LS_LLSC |
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#ifndef LS_LOAD |
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*((uint64_t *)ic->arg[0]) = 1; |
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#endif |
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#endif |
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|
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#endif |
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} |
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#endif |
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|
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|
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static void LS_N(struct cpu *cpu, struct alpha_instr_call *ic) |
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{ |
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unsigned char *page; |
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uint64_t addr = (*((uint64_t *)ic->arg[1])) |
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#ifndef LS_IGNORE_OFFSET |
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+ (int32_t)ic->arg[2] |
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#endif |
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; |
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|
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const uint32_t mask1 = (1 << DYNTRANS_L1N) - 1; |
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const uint32_t mask2 = (1 << DYNTRANS_L2N) - 1; |
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const uint32_t mask3 = (1 << DYNTRANS_L3N) - 1; |
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uint32_t x1, x2, x3, c; |
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struct DYNTRANS_L2_64_TABLE *l2; |
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struct DYNTRANS_L3_64_TABLE *l3; |
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x1 = (addr >> (64-DYNTRANS_L1N)) & mask1; |
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x2 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N)) & mask2; |
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x3 = (addr >> (64-DYNTRANS_L1N-DYNTRANS_L2N-DYNTRANS_L3N)) & mask3; |
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/* fatal("X3: addr=%016"PRIx64" x1=%x x2=%x x3=%x\n", |
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(uint64_t) addr, (int) x1, (int) x2, (int) x3); */ |
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l2 = cpu->cd.DYNTRANS_ARCH.l1_64[x1]; |
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/* fatal(" l2 = %p\n", l2); */ |
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l3 = l2->l3[x2]; |
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/* fatal(" l3 = %p\n", l3); */ |
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#ifdef LS_LOAD |
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page = l3->host_load[x3]; |
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#else |
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page = l3->host_store[x3]; |
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#endif |
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|
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#ifdef LS_UNALIGNED |
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addr &= ~7; |
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#endif |
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|
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#ifdef LS_LLSC |
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#ifdef LS_LOAD |
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/* TODO: cache-line size! */ |
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cpu->cd.alpha.load_linked_addr = addr & ~63; |
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cpu->cd.alpha.ll_flag = 1; |
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#else |
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/* TODO: only invalidate per cache line, not everything! */ |
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if (cpu->cd.alpha.ll_flag == 1) { |
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int i; |
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for (i=0; i<cpu->machine->ncpus; i++) |
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cpu->machine->cpus[i]->cd.alpha.ll_flag = 0; |
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} else { |
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*((uint64_t *)ic->arg[0]) = 0; |
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return; |
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} |
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#endif |
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#endif |
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|
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c = addr & 8191; |
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|
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#ifndef LS_B |
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if (c & |
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#ifdef LS_W |
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1 |
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#endif |
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#ifdef LS_L |
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3 |
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#endif |
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#ifdef LS_Q |
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7 |
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#endif |
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) { |
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LS_GENERIC_N(cpu, ic); |
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return; |
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} |
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else |
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#endif |
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|
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if (page != NULL) { |
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#ifdef LS_LOAD |
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#ifdef HOST_BIG_ENDIAN |
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uint64_t data_x; |
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data_x = page[c]; |
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#ifndef LS_B |
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data_x += (page[c+1] << 8); |
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#ifndef LS_W |
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data_x += (page[c+2] << 16); |
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data_x += ((uint64_t)page[c+3] << 24); |
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#ifndef LS_L |
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data_x += ((uint64_t)page[c+4] << 32); |
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data_x += ((uint64_t)page[c+5] << 40); |
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data_x += ((uint64_t)page[c+6] << 48); |
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data_x += ((uint64_t)page[c+7] << 56); |
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#endif |
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#endif |
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#endif |
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#ifdef LS_L |
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*((uint64_t *)ic->arg[0]) = (int64_t)(int32_t)data_x; |
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#else |
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*((uint64_t *)ic->arg[0]) = data_x; |
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#endif |
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#else |
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#ifdef LS_B |
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*((uint64_t *)ic->arg[0]) = page[c]; |
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#endif |
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#ifdef LS_W |
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uint16_t d = *((uint16_t *) (page + c)); |
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*((uint64_t *)ic->arg[0]) = d; |
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#endif |
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#ifdef LS_L |
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int32_t d = *((int32_t *) (page + c)); |
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*((uint64_t *)ic->arg[0]) = (int64_t)d; |
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#endif |
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#ifdef LS_Q |
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uint64_t d = *((uint64_t *) (page + c)); |
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*((uint64_t *)ic->arg[0]) = d; |
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#endif |
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#endif |
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#else |
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/* Store: */ |
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#ifdef HOST_BIG_ENDIAN |
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uint64_t data_x = *((uint64_t *)ic->arg[0]); |
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page[c] = data_x; |
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#ifndef LS_B |
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page[c+1] = data_x >> 8; |
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#ifndef LS_W |
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page[c+2] = data_x >> 16; |
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page[c+3] = data_x >> 24; |
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#ifndef LS_L |
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page[c+4] = data_x >> 32; |
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page[c+5] = data_x >> 40; |
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page[c+6] = data_x >> 48; |
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page[c+7] = data_x >> 56; |
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#endif |
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#endif |
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#endif |
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#else |
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/* Native byte order: */ |
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#ifdef LS_B |
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page[c] = *((uint64_t *)ic->arg[0]); |
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#endif |
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#ifdef LS_W |
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uint32_t d = *((uint64_t *)ic->arg[0]); |
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*((uint16_t *) (page + c)) = d; |
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#endif |
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#ifdef LS_L |
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uint32_t d = *((uint64_t *)ic->arg[0]); |
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*((uint32_t *) (page + c)) = d; |
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#endif |
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#ifdef LS_Q |
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uint64_t d = *((uint64_t *)ic->arg[0]); |
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*((uint64_t *) (page + c)) = d; |
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#endif |
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#endif |
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|
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#ifdef LS_LLSC |
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#ifndef LS_LOAD |
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*((uint64_t *)ic->arg[0]) = 1; |
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#endif |
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#endif |
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|
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#endif /* !LS_LOAD */ |
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} else |
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LS_GENERIC_N(cpu, ic); |
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} |
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