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Added
Mon Oct 8 16:18:38 2007 UTC
(16 years, 9 months ago)
by
dpavlin
Original Path:
trunk/experiments/new_test_loadstore_a.c
File length: 1030 byte(s)
++ trunk/HISTORY (local)
$Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $
20050628 Continuing the work on the ARM translation engine. end_of_page
works. Experimenting with load/store translation caches
(virtual -> physical -> host).
20050629 More ARM stuff (memory access translation cache, mostly). This
might break a lot of stuff elsewhere, probably some MIPS-
related translation things.
20050630 Many load/stores are now automatically generated and included
into cpu_arm_instr.c; 1024 functions in total (!).
Fixes based on feedback from Alec Voropay: only print 8 hex
digits instead of 16 in some cases when emulating 32-bit
machines; similar 8 vs 16 digit fix for breakpoint addresses;
4Kc has 16 TLB entries, not 48; the MIPS config select1
register is now printed with "reg ,0".
Also changing many other occurances of 16 vs 8 digit output.
Adding cache associativity fields to mips_cpu_types.h; updating
some other cache fields; making the output of
mips_cpu_dumpinfo() look nicer.
Generalizing the bintrans stuff for device accesses to also
work with the new translation system. (This might also break
some MIPS things.)
Adding multi-load/store instructions to the ARM disassembler
and the translator, and some optimizations of various kinds.
20050701 Adding a simple dev_disk (it can read/write sectors from
disk images).
20050712 Adding dev_ether (a simple ethernet send/receive device).
Debugger command "ninstrs" for toggling show_nr_of_instructions
during runtime.
Removing the framebuffer logo.
20050713 Continuing on dev_ether.
Adding a dummy cpu_alpha (again).
20050714 More work on cpu_alpha.
20050715 More work on cpu_alpha. Many instructions work, enough to run
a simple framebuffer fill test (similar to the ARM test).
20050716 More Alpha stuff.
20050717 Minor updates (Alpha stuff).
20050718 Minor updates (Alpha stuff).
20050719 Generalizing some Alpha instructions.
20050720 More Alpha-related updates.
20050721 Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha.
20050722 Alpha-related updates: userland stuff (Hello World using
write() compiled statically for FreeBSD/Alpha runs fine), and
more instructions are now implemented.
20050723 Fixing ldq_u and stq_u.
Adding more instructions (conditional moves, masks, extracts,
shifts).
20050724 More FreeBSD/Alpha userland stuff, and adding some more
instructions (inserts).
20050725 Continuing on the Alpha stuff. (Adding dummy ldt/stt.)
Adding a -A command line option to turn off alignment checks
in some cases (for translated code).
Trying to remove the old bintrans code which updated the pc
and nr_of_executed_instructions for every instruction.
20050726 Making another attempt att removing the pc/nr of instructions
code. This time it worked, huge performance increase for
artificial test code, but performance loss for real-world
code :-( so I'm scrapping that code for now.
Tiny performance increase on Alpha (by using ret instead of
jmp, to play nice with the Alpha's branch prediction) for the
old MIPS bintrans backend.
20050727 Various minor fixes and cleanups.
20050728 Switching from a 2-level virtual to host/physical translation
system for ARM emulation, to a 1-level translation.
Trying to switch from 2-level to 1-level for the MIPS bintrans
system as well (Alpha only, so far), but there is at least one
problem: caches and/or how they work with device mappings.
20050730 Doing the 2-level to 1-level conversion for the i386 backend.
The cache/device bug is still there for R2K/3K :(
Various other minor updates (Malta etc).
The mc146818 clock now updates the UIP bit in a way which works
better with Linux for at least sgimips and Malta emulation.
Beginning the work on refactoring the dyntrans system.
20050731 Continuing the dyntrans refactoring.
Fixing a small but serious host alignment bug in memory_rw.
Adding support for big-endian load/stores to the i386 bintrans
backend.
Another minor i386 bintrans backend update: stores from the
zero register are now one (or two) loads shorter.
The slt and sltu instructions were incorrectly implemented for
the i386 backend; only using them for 32-bit mode for now.
20050801 Continuing the dyntrans refactoring.
Cleanup of the ns16550 serial controller (removing unnecessary
code).
Bugfix (memory corruption bug) in dev_gt, and a patch/hack from
Alec Voropay for Linux/Malta.
20050802 More cleanup/refactoring of the dyntrans subsystem: adding
phys_page pointers to the lookup tables, for quick jumps
between translated pages.
Better fix for the ns16550 device (but still no real FIFO
functionality).
Converting cpu_ppc to the new dyntrans system. This means that
I will have to start from scratch with implementing each
instruction, and figure out how to implement dual 64/32-bit
modes etc.
Removing the URISC CPU family, because it was useless.
20050803 When selecting a machine type, the main type can now be omitted
if the subtype name is unique. (I.e. -E can be omitted.)
Fixing a dyntrans/device update bug. (Writes to offset 0 of
a device could sometimes go unnoticed.)
Adding an experimental "instruction combination" hack for
ARM for memset-like byte fill loops.
20050804 Minor progress on cpu_alpha and related things.
Finally fixing the MIPS dmult/dmultu bugs.
Fixing some minor TODOs.
20050805 Generalizing the 8259 PIC. It now also works with Cobalt
and evbmips emulation, in addition to the x86 hack.
Finally converting the ns16550 device to use devinit.
Continuing the work on the dyntrans system. Thinking about
how to add breakpoints.
20050806 More dyntrans updates. Breakpoints seem to work now.
20050807 Minor updates: cpu_alpha and related things; removing
dev_malta (as it isn't used any more).
Dyntrans: working on general "show trace tree" support.
The trace tree stuff now works with both the old MIPS code and
with newer dyntrans modes. :)
Continuing on Alpha-related stuff (trying to get *BSD to boot
a bit further, adding more instructions, etc).
20050808 Adding a dummy IA64 cpu family, and continuing the refactoring
of the dyntrans system.
Removing the regression test stuff, because it was more or
less useless.
Adding loadlinked/storeconditional type instructions to the
Alpha emulation. (Needed for Linux/alpha. Not very well tested
yet.)
20050809 The function call trace tree now prints a per-function nr of
arguments. (Semi-meaningless, since that data isn't read yet
from the ELFs; some hardcoded symbols such as memcpy() and
strlen() work fine, though.)
More dyntrans refactoring; taking out more of the things that
are common to all cpu families.
20050810 Working on adding support for "dual mode" for PPC dyntrans
(i.e. both 64-bit and 32-bit modes).
(Re)adding some simple PPC instructions.
20050811 Adding a dummy M68K cpu family. The dyntrans system isn't ready
for variable-length ISAs yet, so it's completely bogus so far.
Re-adding more PPC instructions.
Adding a hack to src/file.c which allows OpenBSD/mac68k a.out
kernels to be loaded.
Beginning to add PPC loads/stores. So far they only work in
32-bit mode.
20050812 The configure file option "add_remote" now accepts symbolic
host names, in addition to numeric IPv4 addresses.
Re-adding more PPC instructions.
20050814 Continuing to port back more PPC instructions.
Found and fixed the cache/device write-update bug for 32-bit
MIPS bintrans. :-)
Triggered a really weird and annoying bug in Compaq's C
compiler; ccc sometimes outputs code which loads from an
address _before_ checking whether the pointer was NULL or not.
(I'm not sure how to handle this problem.)
20050815 Removing all of the old x86 instruction execution code; adding
a new (dummy) dyntrans module for x86.
Taking the first steps to extend the dyntrans system to support
variable-length instructions.
Slowly preparing for the next release.
20050816 Adding a dummy SPARC cpu module.
Minor updates (documentation etc) for the release.
============== RELEASE 0.3.5 ==============