/[gxemul]/upstream/0.4.0.1/src/devices/dev_pcic.c
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Contents of /upstream/0.4.0.1/src/devices/dev_pcic.c

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Revision 27 - (show annotations)
Mon Oct 8 16:20:18 2007 UTC (16 years, 8 months ago) by dpavlin
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0.4.0.1
1 /*
2 * Copyright (C) 2005-2006 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * $Id: dev_pcic.c,v 1.16 2006/02/09 20:02:59 debug Exp $
29 *
30 * Intel 82365SL PC Card Interface Controller (called "pcic" by NetBSD).
31 *
32 * TODO: Lots of stuff. This is just a quick hack. Don't rely on it.
33 */
34
35 #include <stdio.h>
36 #include <stdlib.h>
37 #include <string.h>
38
39 #include "cpu.h"
40 #include "device.h"
41 #include "emul.h"
42 #include "machine.h"
43 #include "memory.h"
44 #include "misc.h"
45
46 #include "i82365reg.h"
47 #include "pcmciareg.h"
48
49
50 /* #define debug fatal */
51
52 #define DEV_PCIC_LENGTH 2
53
54 struct pcic_data {
55 int irq_nr;
56 int regnr;
57 };
58
59
60 /*
61 * dev_pcic_cis_access():
62 */
63 DEVICE_ACCESS(pcic_cis)
64 {
65 /* struct pcic_data *d = (struct pcic_data *) extra; */
66 uint64_t idata = 0, odata = 0;
67
68 idata = memory_readmax64(cpu, data, len);
69
70 {
71 #if 0
72 /* SMC, PCM Ethernet Adapter, CIS V1.05 (manufacturer 0x108,
73 product 0x105) */
74 unsigned char x[] = {
75 PCMCIA_CISTPL_DEVICE, 3, PCMCIA_DTYPE_FUNCSPEC, 0xff,0xff,
76 PCMCIA_CISTPL_FUNCID, 2, 0x06, 0x00,
77 PCMCIA_CISTPL_MANFID, 4, 0x08, 0x01, 0x05, 0x01,
78 PCMCIA_CISTPL_VERS_1, 0x26,
79 0x04, 0x01, 0x53, 0x4d, 0x43, 0x00, 0x50, 0x43, 0x4d, 0x20,
80 0x45, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x20, 0x41,
81 0x64, 0x61, 0x70, 0x74, 0x65, 0x72, 0x00, 0x43, 0x49, 0x53,
82 0x20, 0x56, 0x31, 0x2e, 0x30, 0x35, 0x00, 0xff,
83 PCMCIA_CISTPL_CONFIG, 0x0a,
84 0x02, 0x01, 0x00, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0xff,
85 PCMCIA_CISTPL_CFTABLE_ENTRY, 0x0b,
86 0xc1, 0x01, 0x70, 0x50, 0xbc, 0x8e, 0x48, 0x40, 0x00,0x02,0xff,
87 /* unhandled CISTPL 22 */
88 0x22, 0x02, 0x01, 0x02,
89 /* unhandled CISTPL 22 */
90 0x22, 0x05, 0x02, 0x80, 0x96, 0x98, 0x00,
91 /* unhandled CISTPL 22 */
92 0x22, 0x02, 0x03, 0x01,
93 /* unhandled CISTPL 22 */
94 0x22, 0x08, 0x04, 0x06, 0x00, 0x00, 0xc0, 0x2f, 0x48, 0xd2,
95 /* unhandled CISTPL 22 */
96 0x22, 0x02, 0x05, 0x01,
97
98 PCMCIA_CISTPL_END, 0
99 };
100 #endif
101
102 /* From http://www.mail-archive.com/freebsd-current@freebsd.
103 org/msg32550.html */
104 unsigned char x[] = {
105 PCMCIA_CISTPL_DEVICE, 3, 0xdc, 0x00, 0xff,
106 PCMCIA_CISTPL_VERS_1, 0x1a,
107 0x04,0x01,0x20,0x00,0x4e,0x69,0x6e,0x6a,0x61,0x41,0x54,0x41,
108 0x2d,0x00,0x56,0x31,0x2e,0x30,0x00,0x41,0x50,0x30,0x30,0x20,
109 0x00,0xff,
110 PCMCIA_CISTPL_CONFIG, 5,
111 0x01,0x23,0x00,0x02,0x03,
112 PCMCIA_CISTPL_CFTABLE_ENTRY, 0x15,
113 0xe1,0x01,0x3d,0x11,0x55,0x1e,0xfc,0x23,0xf0,0x61,0x80,0x01,
114 0x07,0x86,0x03,0x01,0x30,0x68,0xd0,0x10,0x00,
115 #if 0
116 PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
117 0x22,0x38,0xf0,0x61,0x90,0x01,0x07,0x96,0x03,0x01,0x30,0x68,
118 0xd0,0x10,0x00,
119 PCMCIA_CISTPL_CFTABLE_ENTRY, 0xf,
120 0x23,0x38,0xf0,0x61,0xa0,0x01,0x07,0xa6,0x03,0x01,0x30,0x68,
121 0xd0,0x10,0x00,
122 #endif
123 PCMCIA_CISTPL_NO_LINK, 0,
124
125 PCMCIA_CISTPL_END, 0
126 };
127
128 relative_addr /= 2;
129 if (relative_addr < sizeof(x))
130 odata = x[relative_addr];
131
132 debug("[ dev_pcic_cis_access: blah blah: addr=0x%x ]\n",
133 (int)relative_addr);
134 }
135
136 if (writeflag == MEM_READ)
137 memory_writemax64(cpu, data, len, odata);
138
139 return 1;
140 }
141
142
143 /*
144 * dev_pcic_access():
145 */
146 DEVICE_ACCESS(pcic)
147 {
148 struct pcic_data *d = (struct pcic_data *) extra;
149 uint64_t idata = 0, odata = 0;
150 int controller_nr, socket_nr;
151
152 if (writeflag == MEM_WRITE)
153 idata = memory_readmax64(cpu, data, len);
154
155 controller_nr = d->regnr & 0x80? 1 : 0;
156 socket_nr = d->regnr & 0x40? 1 : 0;
157
158 switch (relative_addr) {
159 case 0: /* Register select: */
160 if (writeflag == MEM_WRITE)
161 d->regnr = idata;
162 else
163 odata = d->regnr;
164 break;
165 case 1: /* Register access: */
166 switch (d->regnr & 0x3f) {
167 case PCIC_IDENT:
168 /* This causes sockets A and B to be present on
169 controller 0, and only socket A on controller 1. */
170 if (controller_nr == 1 && socket_nr == 1)
171 odata = 0;
172 else
173 odata = PCIC_IDENT_IFTYPE_MEM_AND_IO
174 | PCIC_IDENT_REV_I82365SLR1;
175 break;
176 #if 1
177 case PCIC_INTR:
178 odata = PCIC_INTR_IRQ3;
179 break;
180 #endif
181 case PCIC_CSC:
182 odata = PCIC_CSC_GPI;
183 break;
184 case PCIC_IF_STATUS:
185 odata = PCIC_IF_STATUS_READY
186 | PCIC_IF_STATUS_POWERACTIVE;
187 if (controller_nr == 0 && socket_nr == 0)
188 odata |= PCIC_IF_STATUS_CARDDETECT_PRESENT;
189 break;
190 default:
191 if (writeflag == MEM_WRITE) {
192 debug("[ pcic: unimplemented write to "
193 "controller %i socket %c, regnr %i: "
194 "data=0x%02x ]\n", controller_nr,
195 socket_nr? 'B' : 'A',
196 d->regnr & 0x3f, (int)idata);
197 } else {
198 debug("[ pcic: unimplemented read from "
199 "controller %i socket %c, regnr %i ]\n",
200 controller_nr, socket_nr? 'B' : 'A',
201 d->regnr & 0x3f);
202 }
203 }
204 }
205
206 if (writeflag == MEM_READ)
207 memory_writemax64(cpu, data, len, odata);
208
209 return 1;
210 }
211
212
213 DEVINIT(pcic)
214 {
215 struct pcic_data *d = malloc(sizeof(struct pcic_data));
216
217 if (d == NULL) {
218 fprintf(stderr, "out of memory\n");
219 exit(1);
220 }
221 memset(d, 0, sizeof(struct pcic_data));
222 d->irq_nr = devinit->irq_nr;
223
224 memory_device_register(devinit->machine->memory, devinit->name,
225 devinit->addr, DEV_PCIC_LENGTH,
226 dev_pcic_access, (void *)d, DM_DEFAULT, NULL);
227
228 /* TODO: this shouldn't be hardcoded for hpcmips here! */
229 memory_device_register(devinit->machine->memory, "pcic_cis",
230 0x10070000, 0x1000, dev_pcic_cis_access, (void *)d,
231 DM_DEFAULT, NULL);
232
233 /* TODO: find out a good way to specify the address, and the IRQ! */
234 /* IRQ 8 + 32 + 9 */
235 device_add(devinit->machine, "wdc addr=0x14000180 irq=49");
236
237 /* TODO: Linux/MobilePro looks at 0x14000170 and 0x1f0... */
238 /* Yuck. Now there are two. How should this be solved nicely? */
239 device_add(devinit->machine, "wdc addr=0x140001f0 irq=49");
240
241 return 1;
242 }
243

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