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dpavlin |
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/* gxemul: $Id: vripreg.h,v 1.1 2005/04/06 17:13:44 debug Exp $ */ |
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/* $NetBSD: vripreg.h,v 1.8 2003/04/01 02:33:52 igy Exp $ */ |
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#ifndef VRIPREG_H |
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#define VRIPREG_H |
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/*- |
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* Copyright (c) 1999 |
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* Shin Takemura and PocketBSD Project. All rights reserved. |
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* Copyright (c) 2001 SATO Kazumi, All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the PocketBSD project |
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* and its contributors. |
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* 4. Neither the name of the project nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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*/ |
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#define VRIP_NO_ADDR 0x00000000 |
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/* |
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* VR4181 registers |
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*/ |
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#define VR4181_BCU_ADDR 0x0a000000 |
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#define VR4181_DMAAU_ADDR VRIP_NO_ADDR |
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#define VR4181_DCU_ADDR VRIP_NO_ADDR |
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#define VR4181_CMU_ADDR 0x0a000004 |
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#define VR4181_ICU_ADDR 0x0a000080 |
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#define VR4181_PMU_ADDR 0x0a0000a0 |
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#define VR4181_RTC_ADDR 0x0a0000c0 |
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#define VR4181_DSU_ADDR 0x0a0000e0 |
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#define VR4181_GIU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4181_PIU_ADDR 0x0a000122 |
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#define VR4181_AIU_ADDR 0x0a000160 |
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#define VR4181_KIU_ADDR 0x0a000180 |
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#define VR4181_DSIU_ADDR 0x0a0001a0 |
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#define VR4181_LED_ADDR 0x0a000240 |
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#define VR4181_SIU_ADDR 0x0c000010 |
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#define VR4181_HSP_ADDR 0x0a000020 |
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#define VR4181_FIR_ADDR 0x0a000000 /* XXX */ |
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#define VR4181_MEMCON_ADDR 0x0a000300 |
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#define VR4181_ISABRG_ADDR 0x0b0002c0 |
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#define VR4181_ECU_ADDR 0x0b0008e0 |
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#define VR4181_DCU81_ADDR 0x0a000020 |
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#define VR4181_CSI81_ADDR 0x0b000900 |
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#define VR4181_GIU81_ADDR 0x0b000300 |
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#define VR4181_LCD_ADDR 0x0a000400 |
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#define VR4181_SIU1_ADDR 0x0c000000 |
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#define VR4181_SCU_ARR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4181_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4181_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4181_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4181_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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/* |
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* VR4101-4121 registers |
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*/ |
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#define VR4102_BCU_ADDR 0x0b000000 |
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#define VR4102_DMAAU_ADDR 0x0b000020 |
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#define VR4102_DCU_ADDR 0x0b000040 |
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#define VR4102_CMU_ADDR 0x0b000060 |
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#define VR4102_ICU_ADDR 0x0b000080 |
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#define VR4102_PMU_ADDR 0x0b0000a0 |
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#define VR4102_RTC_ADDR 0x0b0000c0 |
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#define VR4102_DSU_ADDR 0x0b0000e0 |
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#define VR4102_GIU_ADDR 0x0b000100 |
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#define VR4102_PIU_ADDR 0x0b000120 |
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#define VR4102_AIU_ADDR 0x0b000160 |
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#define VR4102_KIU_ADDR 0x0b000180 |
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#define VR4102_DSIU_ADDR 0x0b0001a0 |
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#define VR4102_LED_ADDR 0x0b000240 |
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#define VR4102_SIU_ADDR 0x0c000000 |
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#define VR4102_HSP_ADDR 0x0c000020 |
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#define VR4102_FIR_ADDR 0x0b000000 /* XXX */ |
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#define VR4102_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_SCU_ARR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_SDRAMU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_PCI_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_PCICONF_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4102_CSI_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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/* |
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* VR4122 registers |
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*/ |
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#define VR4122_BCU_ADDR 0x0f000000 |
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#define VR4122_DMAAU_ADDR 0x0f000020 |
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#define VR4122_DCU_ADDR 0x0f000040 |
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#define VR4122_CMU_ADDR 0x0f000060 |
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#define VR4122_ICU_ADDR 0x0f000080 |
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#define VR4122_PMU_ADDR 0x0f0000c0 |
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#define VR4122_RTC_ADDR 0x0f000100 |
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#define VR4122_DSU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_GIU_ADDR 0x0f000140 |
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#define VR4122_PIU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_AIU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_KIU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_DSIU_ADDR 0x0f000820 |
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#define VR4122_LED_ADDR 0x0f000180 |
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#define VR4122_SIU_ADDR 0x0f000800 |
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#define VR4122_HSP_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_FIR_ADDR 0x0f000840 /* XXX */ |
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#define VR4122_MEMCON_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_ISABRG_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_ECU_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_DCU81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_CSI81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_GIU81_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_SIU1_ADDR VRIP_NO_ADDR /* XXX: no register */ |
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#define VR4122_SCU_ARR 0x0f001000 |
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#define VR4122_SDRAMU_ADDR 0x0f000400 |
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#define VR4122_PCI_ADDR 0x0f000c00 |
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#define VR4122_PCICONF_ADDR 0x0f000d00 |
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#define VR4122_CSI_ADDR 0x0f0001a0 |
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/* |
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* VRIP base address |
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* |
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* REQUIRE: opt_vr41xx.h, vrcpudef.h |
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*/ |
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#if 0 |
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#include "opt_vr41xx.h" |
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#include <hpcmips/vr/vrcpudef.h> |
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#endif |
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#if defined SINGLE_VRIP_BASE |
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#if defined VRGROUP_4181 |
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#define VRIP_BASE_ADDR 0x0a000000 |
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#define VRIP_BCU_ADDR VR4181_BCU_ADDR |
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#define VRIP_DMAAU_ADDR VR4181_DMAAU_ADDR |
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#define VRIP_DCU_ADDR VR4181_DCU_ADDR |
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#define VRIP_CMU_ADDR VR4181_CMU_ADDR |
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#define VRIP_ICU_ADDR VR4181_ICU_ADDR |
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#define VRIP_PMU_ADDR VR4181_PMU_ADDR |
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#define VRIP_RTC_ADDR VR4181_RTC_ADDR |
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#define VRIP_DSU_ADDR VR4181_DSU_ADDR |
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#define VRIP_GIU_ADDR VR4181_GIU_ADDR |
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#define VRIP_PIU_ADDR VR4181_PIU_ADDR |
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#define VRIP_AIU_ADDR VR4181_AIU_ADDR |
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#define VRIP_KIU_ADDR VR4181_KIU_ADDR |
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#define VRIP_DSIU_ADDR VR4181_DSIU_ADDR |
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#define VRIP_LED_ADDR VR4181_LED_ADDR |
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#define VRIP_SIU_ADDR VR4181_SIU_ADDR |
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#define VRIP_HSP_ADDR VR4181_HSP_ADDR |
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#define VRIP_FIR_ADDR VR4181_FIR_ADDR |
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#define VRIP_MEMCON_ADDR VR4181_MEMCON_ADDR |
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#define VRIP_ISABRG_ADDR VR4181_ISABRG_ADDR |
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#define VRIP_ECU_ADDR VR4181_ECU_ADDR |
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#define VRIP_DCU81_ADDR VR4181_DCU81_ADDR |
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#define VRIP_CSI81_ADDR VR4181_CSI81_ADDR |
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#define VRIP_GIU81_ADDR VR4181_GIU81_ADDR |
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#define VRIP_LCD_ADDR VR4181_LCD_ADDR |
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#define VRIP_SIU1_ADDR VR4181_SIU1_ADDR |
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#define VRIP_SCU_ARR VR4181_SCU_ARR /* XXX: no register */ |
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#define VRIP_SDRAMU_ADDR VR4181_SDRAMU_ADDR /* XXX: no register */ |
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#define VRIP_PCI_ADDR VR4181_PCI_ADDR /* XXX: no register */ |
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#define VRIP_PCICONF_ADDR VR4181_PCICONF_ADDR /* XXX: no register */ |
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#define VRIP_CSI_ADDR VR4181_CSI_ADDR /* XXX: no register */ |
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#endif /* VRGROUP_4181 */ |
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#if defined VRGROUP_4122_4131 |
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#define VRIP_BASE_ADDR 0x0f000000 |
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#define VRIP_BCU_ADDR VR4122_BCU_ADDR |
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#define VRIP_DMAAU_ADDR VR4122_DMAAU_ADDR |
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#define VRIP_DCU_ADDR VR4122_DCU_ADDR |
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#define VRIP_CMU_ADDR VR4122_CMU_ADDR |
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#define VRIP_ICU_ADDR VR4122_ICU_ADDR |
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#define VRIP_PMU_ADDR VR4122_PMU_ADDR |
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#define VRIP_RTC_ADDR VR4122_RTC_ADDR |
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#define VRIP_DSU_ADDR VR4122_DSU_ADDR |
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#define VRIP_GIU_ADDR VR4122_GIU_ADDR |
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#define VRIP_PIU_ADDR VR4122_PIU_ADDR |
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#define VRIP_AIU_ADDR VR4122_AIU_ADDR |
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#define VRIP_KIU_ADDR VR4122_KIU_ADDR |
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#define VRIP_DSIU_ADDR VR4122_DSIU_ADDR |
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#define VRIP_LED_ADDR VR4122_LED_ADDR |
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#define VRIP_SIU_ADDR VR4122_SIU_ADDR |
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#define VRIP_HSP_ADDR VR4122_HSP_ADDR |
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#define VRIP_FIR_ADDR VR4122_FIR_ADDR |
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#define VRIP_MEMCON_ADDR VR4122_MEMCON_ADDR /* XXX: no register */ |
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#define VRIP_ISABRG_ADDR VR4122_ISABRG_ADDR /* XXX: no register */ |
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#define VRIP_ECU_ADDR VR4122_ECU_ADDR /* XXX: no register */ |
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#define VRIP_DCU81_ADDR VR4122_DCU81_ADDR /* XXX: no register */ |
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#define VRIP_CSI81_ADDR VR4122_CSI81_ADDR /* XXX: no register */ |
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#define VRIP_GIU81_ADDR VR4122_CSI81_ADDR /* XXX: no register */ |
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#define VRIP_SIU1_ADDR VR4122_SIU1_ADDR /* XXX: no register */ |
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#define VRIP_SCU_ARR VR4122_SCU_ARR /* XXX: no register */ |
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#define VRIP_SDRAMU_ADDR VR4122_SDRAMU_ADDR /* XXX: no register */ |
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#define VRIP_PCI_ADDR VR4122_PCI_ADDR /* XXX: no register */ |
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#define VRIP_PCICONF_ADDR VR4122_PCICONF_ADDR /* XXX: no register */ |
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#define VRIP_CSI_ADDR VR4122_CSI_ADDR /* XXX: no register */ |
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#endif /* VRGROUP_4122_4131 */ |
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#if defined VRGROUP_4102_4121 |
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#define VRIP_BASE_ADDR 0x0b000000 |
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#define VRIP_BCU_ADDR VR4102_BCU_ADDR |
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#define VRIP_DMAAU_ADDR VR4102_DMAAU_ADDR |
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#define VRIP_DCU_ADDR VR4102_DCU_ADDR |
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#define VRIP_CMU_ADDR VR4102_CMU_ADDR |
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#define VRIP_ICU_ADDR VR4102_ICU_ADDR |
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#define VRIP_PMU_ADDR VR4102_PMU_ADDR |
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#define VRIP_RTC_ADDR VR4102_RTC_ADDR |
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#define VRIP_DSU_ADDR VR4102_DSU_ADDR |
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#define VRIP_GIU_ADDR VR4102_GIU_ADDR |
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#define VRIP_PIU_ADDR VR4102_PIU_ADDR |
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#define VRIP_AIU_ADDR VR4102_AIU_ADDR |
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#define VRIP_KIU_ADDR VR4102_KIU_ADDR |
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#define VRIP_DSIU_ADDR VR4102_DSIU_ADDR |
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#define VRIP_LED_ADDR VR4102_LED_ADDR |
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#define VRIP_SIU_ADDR VR4102_SIU_ADDR |
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#define VRIP_HSP_ADDR VR4102_HSP_ADDR |
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#define VRIP_FIR_ADDR VR4102_FIR_ADDR |
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#define VRIP_MEMCON_ADDR VR4102_MEMCON_ADDR /* XXX: no register */ |
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#define VRIP_ISABRG_ADDR VR4102_ISABRG_ADDR /* XXX: no register */ |
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#define VRIP_ECU_ADDR VR4102_ECU_ADDR /* XXX: no register */ |
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#define VRIP_DCU81_ADDR VR4102_DCU81_ADDR /* XXX: no register */ |
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#define VRIP_CSI81_ADDR VR4102_CSI81_ADDR /* XXX: no register */ |
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#define VRIP_GIU81_ADDR VR4102_GIU81_ADDR /* XXX: no register */ |
| 251 |
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#define VRIP_SIU1_ADDR VR4102_SIU1_ADDR /* XXX: no register */ |
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#define VRIP_SCU_ARR VR4102_SCU_ARR /* XXX: no register */ |
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#define VRIP_SDRAMU_ADDR VR4102_SDRAMU_ADDR /* XXX: no register */ |
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#define VRIP_PCI_ADDR VR4102_PCI_ADDR /* XXX: no register */ |
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#define VRIP_PCICONF_ADDR VR4102_PCICONF_ADDR /* XXX: no register */ |
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#define VRIP_CSI_ADDR VR4102_CSI_ADDR /* XXX: no register */ |
| 257 |
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#endif /* VRGROUP_4102_4121 */ |
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#endif /* SINGLE_VRIP_BASE */ |
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/* |
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* ICU interrupt level |
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*/ |
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/* reserved 62-31 */ |
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#define VRIP_INTR_BCU 25 |
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#define VRIP_INTR_CSI 24 |
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#define VRIP_INTR_SCU 23 |
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#define VRIP_INTR_PCI 22 |
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#define VRIP_INTR_LCD 22 /* 4181 */ |
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#define VRIP_INTR_DSIU 21 |
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#define VRIP_INTR_DCU81 21 /* 4181 */ |
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#define VRIP_INTR_FIR 20 |
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#define VRIP_INTR_TCLK 19 |
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#define VRIP_INTR_CSI81 19 /* 4181 */ |
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#define VRIP_INTR_HSP 18 |
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#define VRIP_INTR_ECU 18 /* 4181 */ |
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#define VRIP_INTR_LED 17 |
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#define VRIP_INTR_RTCL2 16 |
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/* reserved 15,14 */ |
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#define VRIP_INTR_DOZEPIU 13 |
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#define VRIP_INTR_CLKRUN 12 |
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#define VRIP_INTR_SOFT 11 |
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#define VRIP_INTR_WRBERR 10 |
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#define VRIP_INTR_SIU 9 |
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#define VRIP_INTR_GIU 8 |
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#define VRIP_INTR_KIU 7 |
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#define VRIP_INTR_AIU 6 |
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#define VRIP_INTR_PIU 5 |
| 290 |
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/* reserved 4 VRC4171 use this ??? */ |
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#define VRIP_INTR_ETIMER 3 |
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#define VRIP_INTR_RTCL1 2 |
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#define VRIP_INTR_POWER 1 |
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#define VRIP_INTR_BAT 0 |
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| 296 |
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#endif /* VRIPREG_H */ |
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