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#ifndef ARM_CPU_TYPES_H |
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#define ARM_CPU_TYPES_H |
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|
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: arm_cpu_types.h,v 1.4 2005/09/20 21:05:23 debug Exp $ |
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*/ |
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|
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/* See cpu_arm.h for struct arm_cpu_type_def. */ |
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/* See armreg.h for CPU_ID_xxx defines. */ |
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|
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/* Flags: */ |
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#define ARM_NO_MMU 1 |
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#define ARM_DUAL_ENDIAN 2 |
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|
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#include "armreg.h" |
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|
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/* |
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* NOTE: Most of these are bogus! |
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*/ |
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|
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#define ARM_CPU_TYPE_DEFS { \ |
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{ "ARM3", CPU_ID_ARM3, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
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{ "ARM610", CPU_ID_ARM600, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
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{ "ARM610", CPU_ID_ARM610, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
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{ "ARM620", CPU_ID_ARM620, ARM_DUAL_ENDIAN,12, 1, 0, 1 }, \ |
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\ |
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{ "ARM700", CPU_ID_ARM700, 0, 12, 1, 0, 1 }, \ |
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{ "ARM710", CPU_ID_ARM710, 0, 12, 1, 0, 1 }, \ |
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{ "ARM710A", CPU_ID_ARM710A, 0, 12, 1, 0, 1 }, \ |
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{ "ARM720T", CPU_ID_ARM720T, 0, 12, 1, 0, 1 }, \ |
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{ "ARM740T4K", CPU_ID_ARM740T4K,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
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{ "ARM740T8K", CPU_ID_ARM740T8K,ARM_NO_MMU, 13, 1, 0, 1 }, \ |
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{ "ARM7500", CPU_ID_ARM7500, 0, 12, 1, 0, 1 }, \ |
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{ "ARM7500FE", CPU_ID_ARM7500FE,0, 12, 1, 0, 1 }, \ |
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\ |
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{ "ARM810", CPU_ID_ARM810, 0, 12, 1, 0, 1 }, \ |
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{ "ARM920T", CPU_ID_ARM920T, 0, 12, 1, 0, 1 }, \ |
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{ "ARM922T", CPU_ID_ARM922T, 0, 12, 1, 0, 1 }, \ |
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{ "ARM940T", CPU_ID_ARM940T, ARM_NO_MMU, 12, 1, 0, 1 }, \ |
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\ |
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{ "ARM946ES", CPU_ID_ARM946ES,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
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{ "ARM966ES", CPU_ID_ARM966ES,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
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{ "ARM966ESR1", CPU_ID_ARM966ESR1,ARM_NO_MMU, 12, 1, 0, 1 }, \ |
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\ |
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{ "ARM1020E", CPU_ID_ARM1020E,0, 12, 1, 0, 1 }, \ |
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{ "ARM1022ES", CPU_ID_ARM1022ES,0, 12, 1, 0, 1 }, \ |
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{ "ARM1026EJS", CPU_ID_ARM1026EJS,0, 12, 1, 0, 1 }, \ |
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{ "ARM1136JS", CPU_ID_ARM1136JS,0, 12, 1, 0, 1 }, \ |
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{ "ARM1136JSR1",CPU_ID_ARM1136JSR1,0, 12, 1, 0, 1 }, \ |
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\ |
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{ "SA110", CPU_ID_SA110 | 3, 0, 14, 1, 14, 1 }, \ |
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{ "SA1100", CPU_ID_SA1100, 0, 14, 1, 14, 1 }, \ |
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{ "SA1110", CPU_ID_SA1110, 0, 14, 1, 14, 1 }, \ |
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\ |
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{ "TI925T", CPU_ID_TI925T, 0, 14, 1, 14, 1 }, \ |
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{ "IXP1200", CPU_ID_IXP1200, 0, 14, 1, 14, 1 }, \ |
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{ "80200", CPU_ID_80200, 0, 14, 1, 14, 1 }, \ |
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\ |
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{ "PXA210", CPU_ID_PXA210, 0, 16, 1, 0, 1 }, \ |
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{ "PXA210A", CPU_ID_PXA210A, 0, 16, 1, 0, 1 }, \ |
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{ "PXA210B", CPU_ID_PXA210B, 0, 16, 1, 0, 1 }, \ |
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{ "PXA210C", CPU_ID_PXA210C, 0, 16, 1, 0, 1 }, \ |
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{ "PXA250", CPU_ID_PXA250, 0, 16, 1, 0, 1 }, \ |
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{ "PXA250A", CPU_ID_PXA250A, 0, 16, 1, 0, 1 }, \ |
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{ "PXA250B", CPU_ID_PXA250B, 0, 16, 1, 0, 1 }, \ |
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{ "PXA250C", CPU_ID_PXA250C, 0, 16, 1, 0, 1 }, \ |
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{ "PXA27X", CPU_ID_PXA27X, 0, 16, 1, 0, 1 }, \ |
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\ |
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{ "IXP425_255", CPU_ID_IXP425_266, 0, 14, 1, 14, 1 }, \ |
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{ "IXP425_400", CPU_ID_IXP425_400, 0, 14, 1, 14, 1 }, \ |
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{ "IXP425_533", CPU_ID_IXP425_533, 0, 14, 1, 14, 1 }, \ |
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\ |
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{ "80219_400", CPU_ID_80219_400,0, 14, 1, 14, 1 }, \ |
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{ "80219_600", CPU_ID_80219_600,0, 14, 1, 14, 1 }, \ |
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{ "80321_400", CPU_ID_80321_400,0, 14, 1, 14, 1 }, \ |
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{ "80321_400_B0",CPU_ID_80321_400_B0,0, 14, 1, 14, 1 }, \ |
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{ "80321_600", CPU_ID_80321_600,0, 14, 1, 14, 1 }, \ |
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{ "80321_600_B0",CPU_ID_80321_600_B0,0, 14, 1, 14, 1 }, \ |
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\ |
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{ NULL, 0, 0, 0,0, 0,0 } } |
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|
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#endif /* ARM_CPU_TYPES_H */ |
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