/[gxemul]/upstream/0.3.6.2/src/include/memory.h
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Contents of /upstream/0.3.6.2/src/include/memory.h

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Revision 19 - (show annotations)
Mon Oct 8 16:19:16 2007 UTC (16 years, 8 months ago) by dpavlin
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0.3.6.2
1 #ifndef MEMORY_H
2 #define MEMORY_H
3
4 /*
5 * Copyright (C) 2004-2005 Anders Gavare. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 *
31 * $Id: memory.h,v 1.40 2005/10/23 14:24:15 debug Exp $
32 *
33 * Memory controller related functions.
34 */
35
36 #include <sys/types.h>
37 #include <inttypes.h>
38
39 #include "misc.h"
40
41
42 #define DEFAULT_RAM_IN_MB 32
43 #define MAX_DEVICES 24
44
45 #define DEVICE_STATE_TYPE_INT 1
46 #define DEVICE_STATE_TYPE_UINT64_T 2
47
48 struct cpu;
49 struct translation_page_entry;
50
51 /* For bintrans: */
52 #define MAX_QUICK_JUMPS 8
53
54 struct memory {
55 uint64_t physical_max;
56 void *pagetable;
57
58 int n_mmapped_devices;
59 int last_accessed_device;
60 /* The following two might speed up things a little bit. */
61 /* (actually maxaddr is the addr after the last address) */
62 uint64_t mmap_dev_minaddr;
63 uint64_t mmap_dev_maxaddr;
64
65 const char *dev_name[MAX_DEVICES];
66 uint64_t dev_baseaddr[MAX_DEVICES];
67 uint64_t dev_endaddr[MAX_DEVICES]; /* after the end! */
68 uint64_t dev_length[MAX_DEVICES];
69 int dev_flags[MAX_DEVICES];
70 void *dev_extra[MAX_DEVICES];
71 int (*dev_f[MAX_DEVICES])(struct cpu *,struct memory *,
72 uint64_t,unsigned char *,size_t,int,void *);
73 int (*dev_f_state[MAX_DEVICES])(struct cpu *,
74 struct memory *, void *extra, int wf, int nr,
75 int *type, char **namep, void **data, size_t *len);
76 unsigned char *dev_dyntrans_data[MAX_DEVICES];
77
78 int dev_dyntrans_alignment;
79
80 uint64_t dev_dyntrans_write_low[MAX_DEVICES];
81 uint64_t dev_dyntrans_write_high[MAX_DEVICES];
82
83
84 /*
85 * NOTE/TODO: This bintrans was for MIPS only. Ugly. :-/
86 */
87
88 /*
89 * translation_code_chunk_space is a large chunk of (linear) memory
90 * where translated code chunks and translation_entrys are stored.
91 * When this is filled, translation is restart from scratch (by
92 * resetting translation_code_chunk_space_head to 0, and removing all
93 * translation entries).
94 *
95 * (Using a static memory region like this is somewhat inspired by
96 * the QEMU web pages,
97 * http://fabrice.bellard.free.fr/qemu/qemu-tech.html#SEC13)
98 */
99
100 unsigned char *translation_code_chunk_space;
101 size_t translation_code_chunk_space_head;
102
103 int bintrans_32bit_only;
104
105 struct translation_page_entry **translation_page_entry_array;
106
107 unsigned char *quick_jump_host_address[MAX_QUICK_JUMPS];
108 int quick_jump_page_offset[MAX_QUICK_JUMPS];
109 int n_quick_jumps;
110 int quick_jumps_index;
111 };
112
113 #define BITS_PER_PAGETABLE 20
114 #define BITS_PER_MEMBLOCK 20
115 #define MAX_BITS 40
116
117 #define MEM_READ 0
118 #define MEM_WRITE 1
119
120
121 #define CACHE_DATA 0
122 #define CACHE_INSTRUCTION 1
123 #define CACHE_NONE 2
124
125 #define CACHE_FLAGS_MASK 0x3
126
127 #define NO_EXCEPTIONS 16
128 #define PHYSICAL 32
129 #define NO_SEGMENTATION 64 /* for X86 */
130 #define MEMORY_USER_ACCESS 128 /* for ARM, at least */
131
132
133 /* memory.c: */
134 uint64_t memory_readmax64(struct cpu *cpu, unsigned char *buf, int len);
135 void memory_writemax64(struct cpu *cpu, unsigned char *buf, int len,
136 uint64_t data);
137
138 void *zeroed_alloc(size_t s);
139
140 struct memory *memory_new(uint64_t physical_max, int arch);
141
142 int memory_points_to_string(struct cpu *cpu, struct memory *mem,
143 uint64_t addr, int min_string_length);
144 char *memory_conv_to_string(struct cpu *cpu, struct memory *mem,
145 uint64_t addr, char *buf, int bufsize);
146
147 unsigned char *memory_paddr_to_hostaddr(struct memory *mem,
148 uint64_t paddr, int writeflag);
149
150 /* memory_fast_v2h.c: */
151 unsigned char *fast_vaddr_to_hostaddr(struct cpu *cpu, uint64_t vaddr,
152 int writeflag);
153
154 /* MIPS stuff: */
155 int translate_address_mmu3k(struct cpu *cpu, uint64_t vaddr,
156 uint64_t *return_addr, int flags);
157 int translate_address_mmu8k(struct cpu *cpu, uint64_t vaddr,
158 uint64_t *return_addr, int flags);
159 int translate_address_mmu10k(struct cpu *cpu, uint64_t vaddr,
160 uint64_t *return_addr, int flags);
161 int translate_address_mmu4100(struct cpu *cpu, uint64_t vaddr,
162 uint64_t *return_addr, int flags);
163 int translate_address_generic(struct cpu *cpu, uint64_t vaddr,
164 uint64_t *return_addr, int flags);
165
166
167 #define FLAG_WRITEFLAG 1
168 #define FLAG_NOEXCEPTIONS 2
169 #define FLAG_INSTR 4
170
171 int userland_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
172 unsigned char *data, size_t len, int writeflag, int cache);
173 #define MEMORY_ACCESS_FAILED 0
174 #define MEMORY_ACCESS_OK 1
175 #define MEMORY_ACCESS_OK_WRITE 2
176 #define MEMORY_NOT_FULL_PAGE 256
177
178 void memory_device_dyntrans_access(struct cpu *, struct memory *mem,
179 void *extra, uint64_t *low, uint64_t *high);
180
181 void memory_device_register_statefunction(
182 struct memory *mem, void *extra,
183 int (*dev_f_state)(struct cpu *,
184 struct memory *, void *extra, int wf, int nr,
185 int *type, char **namep, void **data, size_t *len));
186
187 void memory_device_register(struct memory *mem, const char *,
188 uint64_t baseaddr, uint64_t len, int (*f)(struct cpu *,
189 struct memory *,uint64_t,unsigned char *,size_t,int,void *),
190 void *extra, int flags, unsigned char *dyntrans_data);
191 void memory_device_remove(struct memory *mem, int i);
192
193 /* Bit flags: */
194 #define MEM_DEFAULT 0
195 #define MEM_DYNTRANS_OK 1
196 #define MEM_DYNTRANS_WRITE_OK 2
197 #define MEM_READING_HAS_NO_SIDE_EFFECTS 4
198 #define MEM_EMULATED_RAM 8
199
200
201 #endif /* MEMORY_H */

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