0.3.5/src/cpu_sparc_instr.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sparc_instr.c,v 1.1 2005/08/16 05:37:10 debug Exp $
 *
 *  SPARC instructions.
 *
 *  Individual functions should keep track of cpu->n_translated_instrs.
 *  (If no instruction was executed, then it should be decreased. If, say, 4
 *  instructions were combined into one function and executed, then it should
 *  be increased by 3.)
 */


/*
 *  nop:  Do nothing.
 */
X(nop)
{
}


/*****************************************************************************/


X(end_of_page)
{
        /*  Update the PC:  (offset 0, but on the next page)  */
        cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) <<
            SPARC_INSTR_ALIGNMENT_SHIFT);
        cpu->pc += (SPARC_IC_ENTRIES_PER_PAGE <<
            SPARC_INSTR_ALIGNMENT_SHIFT);

        /*  Find the new physical page and update the translation pointers:  */
        sparc_pc_to_pointers(cpu);

        /*  end_of_page doesn't count as an executed instruction:  */
        cpu->n_translated_instrs --;
}


/*****************************************************************************/


/*
 *  sparc_combine_instructions():
 *
 *  Combine two or more instructions, if possible, into a single function call.
 */
void COMBINE_INSTRUCTIONS(struct cpu *cpu, struct sparc_instr_call *ic,
        uint32_t addr)
{
        int n_back;
        n_back = (addr >> SPARC_INSTR_ALIGNMENT_SHIFT)
            & (SPARC_IC_ENTRIES_PER_PAGE-1);

        if (n_back >= 1) {
                /*  TODO  */
        }

        /*  TODO: Combine forward as well  */
}


/*****************************************************************************/


/*
 *  sparc_instr_to_be_translated():
 *
 *  Translate an instruction word into an sparc_instr_call. ic is filled in with
 *  valid data for the translated instruction, or a "nothing" instruction if
 *  there was a translation failure. The newly translated instruction is then
 *  executed.
 */
X(to_be_translated)
{
        uint64_t addr, low_pc, tmp_addr;
        uint32_t iword;
        unsigned char *page;
        unsigned char ib[4];
        int main_opcode;
        void (*samepage_function)(struct cpu *, struct sparc_instr_call *);

        /*  Figure out the (virtual) address of the instruction:  */
        low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
            / sizeof(struct sparc_instr_call);
        addr = cpu->pc & ~((SPARC_IC_ENTRIES_PER_PAGE-1)
            << SPARC_INSTR_ALIGNMENT_SHIFT);
        addr += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);
        cpu->pc = addr;
        addr &= ~0x3;

        /*  Read the instruction word from memory:  */
        page = cpu->cd.sparc.host_load[addr >> 12];

        if (page != NULL) {
                /*  fatal("TRANSLATION HIT!\n");  */
                memcpy(ib, page + (addr & 0xfff), sizeof(ib));
        } else {
                /*  fatal("TRANSLATION MISS!\n");  */
                if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
                    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
                        fatal("to_be_translated(): "
                            "read failed: TODO\n");
                        goto bad;
                }
        }

        iword = *((uint32_t *)&ib[0]);

#ifdef HOST_LITTLE_ENDIAN
        iword = ((iword & 0xff) << 24) |
                ((iword & 0xff00) << 8) |
                ((iword & 0xff0000) >> 8) |
                ((iword & 0xff000000) >> 24);
#endif


#define DYNTRANS_TO_BE_TRANSLATED_HEAD
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD


        /*
         *  Translate the instruction:
         */

        main_opcode = iword >> 26;

        switch (main_opcode) {

        default:goto bad;
        }


#define DYNTRANS_TO_BE_TRANSLATED_TAIL
#include "cpu_dyntrans.c" 
#undef  DYNTRANS_TO_BE_TRANSLATED_TAIL
}

1	/*
2	* Copyright (C) 2005 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: cpu_sparc_instr.c,v 1.1 2005/08/16 05:37:10 debug Exp $
29	*
30	* SPARC instructions.
31	*
32	* Individual functions should keep track of cpu->n_translated_instrs.
33	* (If no instruction was executed, then it should be decreased. If, say, 4
34	* instructions were combined into one function and executed, then it should
35	* be increased by 3.)
36	*/
37
38
39	/*
40	* nop: Do nothing.
41	*/
42	X(nop)
43	{
44	}
45
46
47	/*****************************************************************************/
48
49
50	X(end_of_page)
51	{
52	/* Update the PC: (offset 0, but on the next page) */
53	cpu->pc &= ~((SPARC_IC_ENTRIES_PER_PAGE-1) <<
54	SPARC_INSTR_ALIGNMENT_SHIFT);
55	cpu->pc += (SPARC_IC_ENTRIES_PER_PAGE <<
56	SPARC_INSTR_ALIGNMENT_SHIFT);
57
58	/* Find the new physical page and update the translation pointers: */
59	sparc_pc_to_pointers(cpu);
60
61	/* end_of_page doesn't count as an executed instruction: */
62	cpu->n_translated_instrs --;
63	}
64
65
66	/*****************************************************************************/
67
68
69	/*
70	* sparc_combine_instructions():
71	*
72	* Combine two or more instructions, if possible, into a single function call.
73	*/
74	void COMBINE_INSTRUCTIONS(struct cpu cpu, struct sparc_instr_call ic,
75	uint32_t addr)
76	{
77	int n_back;
78	n_back = (addr >> SPARC_INSTR_ALIGNMENT_SHIFT)
79	& (SPARC_IC_ENTRIES_PER_PAGE-1);
80
81	if (n_back >= 1) {
82	/* TODO */
83	}
84
85	/* TODO: Combine forward as well */
86	}
87
88
89	/*****************************************************************************/
90
91
92	/*
93	* sparc_instr_to_be_translated():
94	*
95	* Translate an instruction word into an sparc_instr_call. ic is filled in with
96	* valid data for the translated instruction, or a "nothing" instruction if
97	* there was a translation failure. The newly translated instruction is then
98	* executed.
99	*/
100	X(to_be_translated)
101	{
102	uint64_t addr, low_pc, tmp_addr;
103	uint32_t iword;
104	unsigned char *page;
105	unsigned char ib[4];
106	int main_opcode;
107	void (samepage_function)(struct cpu , struct sparc_instr_call *);
108
109	/* Figure out the (virtual) address of the instruction: */
110	low_pc = ((size_t)ic - (size_t)cpu->cd.sparc.cur_ic_page)
111	/ sizeof(struct sparc_instr_call);
112	addr = cpu->pc & ~((SPARC_IC_ENTRIES_PER_PAGE-1)
113	<< SPARC_INSTR_ALIGNMENT_SHIFT);
114	addr += (low_pc << SPARC_INSTR_ALIGNMENT_SHIFT);
115	cpu->pc = addr;
116	addr &= ~0x3;
117
118	/* Read the instruction word from memory: */
119	page = cpu->cd.sparc.host_load[addr >> 12];
120
121	if (page != NULL) {
122	/* fatal("TRANSLATION HIT!\n"); */
123	memcpy(ib, page + (addr & 0xfff), sizeof(ib));
124	} else {
125	/* fatal("TRANSLATION MISS!\n"); */
126	if (!cpu->memory_rw(cpu, cpu->mem, addr, ib,
127	sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
128	fatal("to_be_translated(): "
129	"read failed: TODO\n");
130	goto bad;
131	}
132	}
133
134	iword = ((uint32_t )&ib[0]);
135
136	#ifdef HOST_LITTLE_ENDIAN
137	iword = ((iword & 0xff) << 24) \|
138	((iword & 0xff00) << 8) \|
139	((iword & 0xff0000) >> 8) \|
140	((iword & 0xff000000) >> 24);
141	#endif
142
143
144	#define DYNTRANS_TO_BE_TRANSLATED_HEAD
145	#include "cpu_dyntrans.c"
146	#undef DYNTRANS_TO_BE_TRANSLATED_HEAD
147
148
149	/*
150	* Translate the instruction:
151	*/
152
153	main_opcode = iword >> 26;
154
155	switch (main_opcode) {
156
157	default:goto bad;
158	}
159
160
161	#define DYNTRANS_TO_BE_TRANSLATED_TAIL
162	#include "cpu_dyntrans.c"
163	#undef DYNTRANS_TO_BE_TRANSLATED_TAIL
164	}
165