0.3.5/src/cpu_sparc.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_sparc.c,v 1.13 2005/08/16 05:37:10 debug Exp $
 *
 *  SPARC CPU emulation.
 */

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>

#include "misc.h"


#ifndef ENABLE_SPARC


#include "cpu_sparc.h"


/*
 *  sparc_cpu_family_init():
 *
 *  Bogus function.
 */
int sparc_cpu_family_init(struct cpu_family *fp)
{
        return 0;
}


#else   /*  ENABLE_SPARC  */


#include "cpu.h"
#include "cpu_sparc.h"
#include "machine.h"
#include "memory.h"
#include "symbol.h"

#define DYNTRANS_DUALMODE_32
#define DYNTRANS_32
#include "tmp_sparc_head.c"


/*
 *  sparc_cpu_new():
 *
 *  Create a new SPARC cpu object.
 *
 *  Returns 1 on success, 0 if there was no matching SPARC processor with
 *  this cpu_type_name.
 */
int sparc_cpu_new(struct cpu *cpu, struct memory *mem, struct machine *machine,
        int cpu_id, char *cpu_type_name)
{
        if (strcasecmp(cpu_type_name, "SPARCv9") != 0)
                return 0;

        cpu->memory_rw = sparc_memory_rw;
        cpu->update_translation_table = sparc_update_translation_table;
        cpu->invalidate_translation_caches_paddr =
            sparc_invalidate_translation_caches_paddr;
        cpu->invalidate_code_translation_caches =
            sparc_invalidate_code_translation_caches;

        cpu->byte_order = EMUL_BIG_ENDIAN;
        cpu->is_32bit = 0;

        /*  Only show name and caches etc for CPU nr 0 (in SMP machines):  */
        if (cpu_id == 0) {
                debug("%s", cpu->name);
        }

        return 1;
}


/*
 *  sparc_cpu_list_available_types():
 *
 *  Print a list of available SPARC CPU types.
 */
void sparc_cpu_list_available_types(void)
{
        debug("SPARCv9\n");
        /*  TODO  */
}


/*
 *  sparc_cpu_dumpinfo():
 */
void sparc_cpu_dumpinfo(struct cpu *cpu)
{
        debug("\n");
        /*  TODO  */
}


/*
 *  sparc_cpu_register_dump():
 *
 *  Dump cpu registers in a relatively readable format.
 *
 *  gprs: set to non-zero to dump GPRs and some special-purpose registers.
 *  coprocs: set bit 0..3 to dump registers in coproc 0..3.
 */
void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
{
        char *symbol;
        uint64_t offset, tmp;
        int i, x = cpu->cpu_id;
        int bits32 = 0;

        if (gprs) {
                /*  Special registers (pc, ...) first:  */
                symbol = get_symbol_name(&cpu->machine->symbol_context,
                    cpu->pc, &offset);

                debug("cpu%i: pc  = 0x", x);
                if (bits32)
                        debug("%08x", (int)cpu->pc);
                else
                        debug("%016llx", (long long)cpu->pc);
                debug("  <%s>\n", symbol != NULL? symbol : " no symbol ");

                /*  TODO  */
        }
}


/*
 *  sparc_cpu_register_match():
 */
void sparc_cpu_register_match(struct machine *m, char *name,
        int writeflag, uint64_t *valuep, int *match_register)
{
        int cpunr = 0;

        /*  CPU number:  */

        /*  TODO  */

        /*  Register name:  */
        if (strcasecmp(name, "pc") == 0) {
                if (writeflag) {
                        m->cpus[cpunr]->pc = *valuep;
                } else
                        *valuep = m->cpus[cpunr]->pc;
                *match_register = 1;
        }
}


/*
 *  sparc_cpu_show_full_statistics():
 *
 *  Show detailed statistics on opcode usage on each cpu.
 */
void sparc_cpu_show_full_statistics(struct machine *m)
{
        fatal("sparc_cpu_show_full_statistics(): TODO\n");
}


/*
 *  sparc_cpu_tlbdump():
 *
 *  Called from the debugger to dump the TLB in a readable format.
 *  x is the cpu number to dump, or -1 to dump all CPUs.
 *
 *  If rawflag is nonzero, then the TLB contents isn't formated nicely,
 *  just dumped.
 */
void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag)
{
        fatal("sparc_cpu_tlbdump(): TODO\n");
}


/*
 *  sparc_cpu_interrupt():
 */
int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
{
        fatal("sparc_cpu_interrupt(): TODO\n");
        return 0;
}


/*
 *  sparc_cpu_interrupt_ack():
 */
int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
{
        /*  fatal("sparc_cpu_interrupt_ack(): TODO\n");  */
        return 0;
}


/*
 *  sparc_cpu_disassemble_instr():
 *
 *  Convert an instruction word into human readable format, for instruction
 *  tracing.
 *
 *  If running is 1, cpu->pc should be the address of the instruction.
 *
 *  If running is 0, things that depend on the runtime environment (eg.
 *  register contents) will not be shown, and addr will be used instead of
 *  cpu->pc for relative addresses.
 */
int sparc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
        int running, uint64_t dumpaddr, int bintrans)
{
        uint64_t offset, addr;
        uint32_t iword;
        int hi6;
        char *symbol, *mnem = "ERROR";

        if (running)
                dumpaddr = cpu->pc;

        symbol = get_symbol_name(&cpu->machine->symbol_context,
            dumpaddr, &offset);
        if (symbol != NULL && offset==0)
                debug("<%s>\n", symbol);

        if (cpu->machine->ncpus > 1 && running)
                debug("cpu%i: ", cpu->cpu_id);

/*      if (cpu->cd.sparc.bits == 32)
                debug("%08x", (int)dumpaddr);
        else
*/              debug("%016llx", (long long)dumpaddr);

        iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
            + instr[3];

        debug(": %08x\t", iword);

        /*
         *  Decode the instruction:
         */

        hi6 = iword >> 26;

        switch (hi6) {
        default:
                /*  TODO  */
                debug("unimplemented hi6 = 0x%02x", hi6);
        }

        debug("\n");
        return sizeof(iword);
}


#include "tmp_sparc_tail.c"


#endif  /*  ENABLE_SPARC  */
1	/*
2	* Copyright (C) 2005 Anders Gavare. All rights reserved.
3	*
4	* Redistribution and use in source and binary forms, with or without
5	* modification, are permitted provided that the following conditions are met:
6	*
7	* 1. Redistributions of source code must retain the above copyright
8	* notice, this list of conditions and the following disclaimer.
9	* 2. Redistributions in binary form must reproduce the above copyright
10	* notice, this list of conditions and the following disclaimer in the
11	* documentation and/or other materials provided with the distribution.
12	* 3. The name of the author may not be used to endorse or promote products
13	* derived from this software without specific prior written permission.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.
26	*
27	*
28	* $Id: cpu_sparc.c,v 1.13 2005/08/16 05:37:10 debug Exp $
29	*
30	* SPARC CPU emulation.
31	*/
32
33	#include <stdio.h>
34	#include <stdlib.h>
35	#include <string.h>
36	#include <ctype.h>
37
38	#include "misc.h"
39
40
41	#ifndef ENABLE_SPARC
42
43
44	#include "cpu_sparc.h"
45
46
47	/*
48	* sparc_cpu_family_init():
49	*
50	* Bogus function.
51	*/
52	int sparc_cpu_family_init(struct cpu_family *fp)
53	{
54	return 0;
55	}
56
57
58	#else /* ENABLE_SPARC */
59
60
61	#include "cpu.h"
62	#include "cpu_sparc.h"
63	#include "machine.h"
64	#include "memory.h"
65	#include "symbol.h"
66
67	#define DYNTRANS_DUALMODE_32
68	#define DYNTRANS_32
69	#include "tmp_sparc_head.c"
70
71
72	/*
73	* sparc_cpu_new():
74	*
75	* Create a new SPARC cpu object.
76	*
77	* Returns 1 on success, 0 if there was no matching SPARC processor with
78	* this cpu_type_name.
79	*/
80	int sparc_cpu_new(struct cpu cpu, struct memory mem, struct machine *machine,
81	int cpu_id, char *cpu_type_name)
82	{
83	if (strcasecmp(cpu_type_name, "SPARCv9") != 0)
84	return 0;
85
86	cpu->memory_rw = sparc_memory_rw;
87	cpu->update_translation_table = sparc_update_translation_table;
88	cpu->invalidate_translation_caches_paddr =
89	sparc_invalidate_translation_caches_paddr;
90	cpu->invalidate_code_translation_caches =
91	sparc_invalidate_code_translation_caches;
92
93	cpu->byte_order = EMUL_BIG_ENDIAN;
94	cpu->is_32bit = 0;
95
96	/* Only show name and caches etc for CPU nr 0 (in SMP machines): */
97	if (cpu_id == 0) {
98	debug("%s", cpu->name);
99	}
100
101	return 1;
102	}
103
104
105	/*
106	* sparc_cpu_list_available_types():
107	*
108	* Print a list of available SPARC CPU types.
109	*/
110	void sparc_cpu_list_available_types(void)
111	{
112	debug("SPARCv9\n");
113	/* TODO */
114	}
115
116
117	/*
118	* sparc_cpu_dumpinfo():
119	*/
120	void sparc_cpu_dumpinfo(struct cpu *cpu)
121	{
122	debug("\n");
123	/* TODO */
124	}
125
126
127	/*
128	* sparc_cpu_register_dump():
129	*
130	* Dump cpu registers in a relatively readable format.
131	*
132	* gprs: set to non-zero to dump GPRs and some special-purpose registers.
133	* coprocs: set bit 0..3 to dump registers in coproc 0..3.
134	*/
135	void sparc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs)
136	{
137	char *symbol;
138	uint64_t offset, tmp;
139	int i, x = cpu->cpu_id;
140	int bits32 = 0;
141
142	if (gprs) {
143	/* Special registers (pc, ...) first: */
144	symbol = get_symbol_name(&cpu->machine->symbol_context,
145	cpu->pc, &offset);
146
147	debug("cpu%i: pc = 0x", x);
148	if (bits32)
149	debug("%08x", (int)cpu->pc);
150	else
151	debug("%016llx", (long long)cpu->pc);
152	debug(" <%s>\n", symbol != NULL? symbol : " no symbol ");
153
154	/* TODO */
155	}
156	}
157
158
159	/*
160	* sparc_cpu_register_match():
161	*/
162	void sparc_cpu_register_match(struct machine m, char name,
163	int writeflag, uint64_t valuep, int match_register)
164	{
165	int cpunr = 0;
166
167	/* CPU number: */
168
169	/* TODO */
170
171	/* Register name: */
172	if (strcasecmp(name, "pc") == 0) {
173	if (writeflag) {
174	m->cpus[cpunr]->pc = *valuep;
175	} else
176	*valuep = m->cpus[cpunr]->pc;
177	*match_register = 1;
178	}
179	}
180
181
182	/*
183	* sparc_cpu_show_full_statistics():
184	*
185	* Show detailed statistics on opcode usage on each cpu.
186	*/
187	void sparc_cpu_show_full_statistics(struct machine *m)
188	{
189	fatal("sparc_cpu_show_full_statistics(): TODO\n");
190	}
191
192
193	/*
194	* sparc_cpu_tlbdump():
195	*
196	* Called from the debugger to dump the TLB in a readable format.
197	* x is the cpu number to dump, or -1 to dump all CPUs.
198	*
199	* If rawflag is nonzero, then the TLB contents isn't formated nicely,
200	* just dumped.
201	*/
202	void sparc_cpu_tlbdump(struct machine *m, int x, int rawflag)
203	{
204	fatal("sparc_cpu_tlbdump(): TODO\n");
205	}
206
207
208	/*
209	* sparc_cpu_interrupt():
210	*/
211	int sparc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr)
212	{
213	fatal("sparc_cpu_interrupt(): TODO\n");
214	return 0;
215	}
216
217
218	/*
219	* sparc_cpu_interrupt_ack():
220	*/
221	int sparc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr)
222	{
223	/* fatal("sparc_cpu_interrupt_ack(): TODO\n"); */
224	return 0;
225	}
226
227
228	/*
229	* sparc_cpu_disassemble_instr():
230	*
231	* Convert an instruction word into human readable format, for instruction
232	* tracing.
233	*
234	* If running is 1, cpu->pc should be the address of the instruction.
235	*
236	* If running is 0, things that depend on the runtime environment (eg.
237	* register contents) will not be shown, and addr will be used instead of
238	* cpu->pc for relative addresses.
239	*/
240	int sparc_cpu_disassemble_instr(struct cpu cpu, unsigned char instr,
241	int running, uint64_t dumpaddr, int bintrans)
242	{
243	uint64_t offset, addr;
244	uint32_t iword;
245	int hi6;
246	char symbol, mnem = "ERROR";
247
248	if (running)
249	dumpaddr = cpu->pc;
250
251	symbol = get_symbol_name(&cpu->machine->symbol_context,
252	dumpaddr, &offset);
253	if (symbol != NULL && offset==0)
254	debug("<%s>\n", symbol);
255
256	if (cpu->machine->ncpus > 1 && running)
257	debug("cpu%i: ", cpu->cpu_id);
258
259	/* if (cpu->cd.sparc.bits == 32)
260	debug("%08x", (int)dumpaddr);
261	else
262	*/ debug("%016llx", (long long)dumpaddr);
263
264	iword = (instr[0] << 24) + (instr[1] << 16) + (instr[2] << 8)
265	+ instr[3];
266
267	debug(": %08x\t", iword);
268
269	/*
270	* Decode the instruction:
271	*/
272
273	hi6 = iword >> 26;
274
275	switch (hi6) {
276	default:
277	/* TODO */
278	debug("unimplemented hi6 = 0x%02x", hi6);
279	}
280
281	debug("\n");
282	return sizeof(iword);
283	}
284
285
286	#include "tmp_sparc_tail.c"
287
288
289	#endif /* ENABLE_SPARC */