0.3.5/src/cpu_ia64_instr.c

/*
 *  Copyright (C) 2005  Anders Gavare.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are met:
 *
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright  
 *     notice, this list of conditions and the following disclaimer in the 
 *     documentation and/or other materials provided with the distribution.
 *  3. The name of the author may not be used to endorse or promote products
 *     derived from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 *  ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 *  ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE   
 *  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 *  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 *  OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 *  HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 *  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 *  OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 *
 *  $Id: cpu_ia64_instr.c,v 1.3 2005/08/14 23:44:22 debug Exp $
 *
 *  IA64 instructions.
 *
 *  Individual functions should keep track of cpu->n_translated_instrs.
 *  (If no instruction was executed, then it should be decreased. If, say, 4
 *  instructions were combined into one function and executed, then it should
 *  be increased by 3.)
 */


/*
 *  nop:  Do nothing.
 */
X(nop)
{
}


/*****************************************************************************/


X(end_of_page)
{
        /*  Update the PC:  (offset 0, but on the next page)  */
        cpu->pc &= ~((IA64_IC_ENTRIES_PER_PAGE-1) << 4);
        cpu->pc += (IA64_IC_ENTRIES_PER_PAGE << 4);

        /*  Find the new physical page and update the translation pointers:  */
        ia64_pc_to_pointers(cpu);

        /*  end_of_page doesn't count as an executed instruction:  */
        cpu->n_translated_instrs --;
}


/*****************************************************************************/


/*
 *  ia64_combine_instructions():
 *
 *  Combine two or more instructions, if possible, into a single function call.
 */
void ia64_combine_instructions(struct cpu *cpu, struct ia64_instr_call *ic,
        uint64_t addr)
{
        int n_back;
        n_back = (addr >> 4) & (IA64_IC_ENTRIES_PER_PAGE-1);

        if (n_back >= 1) {
        }

        /*  TODO: Combine forward as well  */
}


/*****************************************************************************/


/*
 *  ia64_instr_to_be_translated():
 *
 *  Translate an instruction word into an ia64_instr_call. ic is filled in with
 *  valid data for the translated instruction, or a "nothing" instruction if
 *  there was a translation failure. The newly translated instruction is then
 *  executed.
 */
X(to_be_translated)
{
        uint64_t addr, low_pc;
        struct ia64_vph_page *vph_p;
        unsigned char *page;
        unsigned char ib[16];

        /*  Figure out the (virtual) address of the instruction:  */
        low_pc = ((size_t)ic - (size_t)cpu->cd.ia64.cur_ic_page)
            / sizeof(struct ia64_instr_call);
        addr = cpu->pc & ~((IA64_IC_ENTRIES_PER_PAGE-1)
            << IA64_INSTR_ALIGNMENT_SHIFT);
        addr += (low_pc << IA64_INSTR_ALIGNMENT_SHIFT);
        addr &= ~0xf;
        cpu->pc = addr;

        /*  Read the instruction word from memory:  */
#if 0
        if ((addr >> _TOPSHIFT) == 0) {
                vph_p = cpu->cd.alpha.vph_table0[(addr >>
                    ALPHA_LEVEL0_SHIFT) & 8191];
                page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];
        } else if ((addr >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) {
                vph_p = cpu->cd.alpha.vph_table0_kernel[(addr >>
                    ALPHA_LEVEL0_SHIFT) & 8191];
                page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];
        } else
                page = NULL;

        if (page != NULL) {
                /*  fatal("TRANSLATION HIT!\n");  */
                memcpy(ib, page + (addr & 8191), sizeof(ib));
        } else
#endif
 {
                /*  fatal("TRANSLATION MISS!\n");  */
                if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
                    sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
                        fatal("to_be_translated(): read failed: TODO\n");
                        goto bad;
                }
        }


#define DYNTRANS_TO_BE_TRANSLATED_HEAD
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_HEAD


fatal("[ UNIMPLEMENTED IA64 instruction ]\n");
goto bad;


#define DYNTRANS_TO_BE_TRANSLATED_TAIL
#include "cpu_dyntrans.c"
#undef  DYNTRANS_TO_BE_TRANSLATED_TAIL
}

1	dpavlin	12	/*
2			* Copyright (C) 2005 Anders Gavare. All rights reserved.
3			*
4			* Redistribution and use in source and binary forms, with or without
5			* modification, are permitted provided that the following conditions are met:
6			*
7			* 1. Redistributions of source code must retain the above copyright
8			* notice, this list of conditions and the following disclaimer.
9			* 2. Redistributions in binary form must reproduce the above copyright
10			* notice, this list of conditions and the following disclaimer in the
11			* documentation and/or other materials provided with the distribution.
12			* 3. The name of the author may not be used to endorse or promote products
13			* derived from this software without specific prior written permission.
14			*
15			* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16			* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17			* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18			* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19			* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20			* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21			* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22			* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23			* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24			* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25			* SUCH DAMAGE.
26			*
27			*
28			* $Id: cpu_ia64_instr.c,v 1.3 2005/08/14 23:44:22 debug Exp $
29			*
30			* IA64 instructions.
31			*
32			* Individual functions should keep track of cpu->n_translated_instrs.
33			* (If no instruction was executed, then it should be decreased. If, say, 4
34			* instructions were combined into one function and executed, then it should
35			* be increased by 3.)
36			*/
37
38
39			/*
40			* nop: Do nothing.
41			*/
42			X(nop)
43			{
44			}
45
46
47			/*****************************************************************************/
48
49
50			X(end_of_page)
51			{
52			/* Update the PC: (offset 0, but on the next page) */
53			cpu->pc &= ~((IA64_IC_ENTRIES_PER_PAGE-1) << 4);
54			cpu->pc += (IA64_IC_ENTRIES_PER_PAGE << 4);
55
56			/* Find the new physical page and update the translation pointers: */
57			ia64_pc_to_pointers(cpu);
58
59			/* end_of_page doesn't count as an executed instruction: */
60			cpu->n_translated_instrs --;
61			}
62
63
64			/*****************************************************************************/
65
66
67			/*
68			* ia64_combine_instructions():
69			*
70			* Combine two or more instructions, if possible, into a single function call.
71			*/
72			void ia64_combine_instructions(struct cpu cpu, struct ia64_instr_call ic,
73			uint64_t addr)
74			{
75			int n_back;
76			n_back = (addr >> 4) & (IA64_IC_ENTRIES_PER_PAGE-1);
77
78			if (n_back >= 1) {
79			}
80
81			/* TODO: Combine forward as well */
82			}
83
84
85			/*****************************************************************************/
86
87
88			/*
89			* ia64_instr_to_be_translated():
90			*
91			* Translate an instruction word into an ia64_instr_call. ic is filled in with
92			* valid data for the translated instruction, or a "nothing" instruction if
93			* there was a translation failure. The newly translated instruction is then
94			* executed.
95			*/
96			X(to_be_translated)
97			{
98			uint64_t addr, low_pc;
99			struct ia64_vph_page *vph_p;
100			unsigned char *page;
101			unsigned char ib[16];
102
103			/* Figure out the (virtual) address of the instruction: */
104			low_pc = ((size_t)ic - (size_t)cpu->cd.ia64.cur_ic_page)
105			/ sizeof(struct ia64_instr_call);
106			addr = cpu->pc & ~((IA64_IC_ENTRIES_PER_PAGE-1)
107			<< IA64_INSTR_ALIGNMENT_SHIFT);
108			addr += (low_pc << IA64_INSTR_ALIGNMENT_SHIFT);
109			addr &= ~0xf;
110			cpu->pc = addr;
111
112			/* Read the instruction word from memory: */
113			#if 0
114			if ((addr >> _TOPSHIFT) == 0) {
115			vph_p = cpu->cd.alpha.vph_table0[(addr >>
116			ALPHA_LEVEL0_SHIFT) & 8191];
117			page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];
118			} else if ((addr >> ALPHA_TOPSHIFT) == ALPHA_TOP_KERNEL) {
119			vph_p = cpu->cd.alpha.vph_table0_kernel[(addr >>
120			ALPHA_LEVEL0_SHIFT) & 8191];
121			page = vph_p->host_load[(addr >> ALPHA_LEVEL1_SHIFT) & 8191];
122			} else
123			page = NULL;
124
125			if (page != NULL) {
126			/* fatal("TRANSLATION HIT!\n"); */
127			memcpy(ib, page + (addr & 8191), sizeof(ib));
128			} else
129			#endif
130			{
131			/* fatal("TRANSLATION MISS!\n"); */
132			if (!cpu->memory_rw(cpu, cpu->mem, addr, &ib[0],
133			sizeof(ib), MEM_READ, CACHE_INSTRUCTION)) {
134			fatal("to_be_translated(): read failed: TODO\n");
135			goto bad;
136			}
137			}
138
139
140			#define DYNTRANS_TO_BE_TRANSLATED_HEAD
141			#include "cpu_dyntrans.c"
142			#undef DYNTRANS_TO_BE_TRANSLATED_HEAD
143
144
145			fatal("[ UNIMPLEMENTED IA64 instruction ]\n");
146			goto bad;
147
148
149			#define DYNTRANS_TO_BE_TRANSLATED_TAIL
150			#include "cpu_dyntrans.c"
151			#undef DYNTRANS_TO_BE_TRANSLATED_TAIL
152			}
153