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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_arm.c,v 1.57 2005/08/12 20:20:28 debug Exp $ |
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* |
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* ARM CPU emulation. |
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* |
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* Sources of information refered to in cpu_arm*.c: |
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* |
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* (1) http://www.pinknoise.demon.co.uk/ARMinstrs/ARMinstrs.html |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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#include <ctype.h> |
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|
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#include "misc.h" |
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|
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|
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#ifndef ENABLE_ARM |
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|
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|
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#include "cpu_arm.h" |
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|
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|
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/* |
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* arm_cpu_family_init(): |
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* |
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* Bogus, when ENABLE_ARM isn't defined. |
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*/ |
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int arm_cpu_family_init(struct cpu_family *fp) |
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{ |
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return 0; |
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} |
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|
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|
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#else /* ENABLE_ARM */ |
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|
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|
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#include "cpu.h" |
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#include "cpu_arm.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "symbol.h" |
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|
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#define DYNTRANS_32 |
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#include "tmp_arm_head.c" |
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|
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|
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/* ARM symbolic register names and condition strings: */ |
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static char *arm_regname[N_ARM_REGS] = ARM_REG_NAMES; |
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static char *arm_condition_string[16] = ARM_CONDITION_STRINGS; |
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|
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/* Data Processing Instructions: */ |
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static char *arm_dpiname[16] = ARM_DPI_NAMES; |
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static int arm_dpi_uses_d[16] = { 1,1,1,1,1,1,1,1,0,0,0,0,1,1,1,1 }; |
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static int arm_dpi_uses_n[16] = { 1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,0 }; |
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|
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|
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/* |
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* arm_cpu_new(): |
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* |
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* Create a new ARM cpu object by filling the CPU struct. |
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* Return 1 on success, 0 if cpu_type_name isn't a valid ARM processor. |
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*/ |
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int arm_cpu_new(struct cpu *cpu, struct memory *mem, |
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struct machine *machine, int cpu_id, char *cpu_type_name) |
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{ |
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if (strcmp(cpu_type_name, "ARM") != 0) |
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return 0; |
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|
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cpu->memory_rw = arm_memory_rw; |
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cpu->update_translation_table = arm_update_translation_table; |
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cpu->invalidate_translation_caches_paddr = |
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arm_invalidate_translation_caches_paddr; |
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cpu->invalidate_code_translation_caches = |
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arm_invalidate_code_translation_caches; |
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cpu->is_32bit = 1; |
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|
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cpu->cd.arm.flags = ARM_FLAG_I | ARM_FLAG_F | ARM_MODE_USR32; |
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|
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/* Only show name and caches etc for CPU nr 0: */ |
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if (cpu_id == 0) { |
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debug("%s", cpu->name); |
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} |
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|
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return 1; |
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} |
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|
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|
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/* |
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* arm_cpu_dumpinfo(): |
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*/ |
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void arm_cpu_dumpinfo(struct cpu *cpu) |
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{ |
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/* TODO */ |
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debug("\n"); |
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} |
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|
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|
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/* |
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* arm_cpu_list_available_types(): |
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* |
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* Print a list of available ARM CPU types. |
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*/ |
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void arm_cpu_list_available_types(void) |
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{ |
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/* TODO */ |
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|
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debug("ARM\n"); |
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} |
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|
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|
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/* |
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* arm_cpu_register_match(): |
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*/ |
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void arm_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register) |
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{ |
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int i, cpunr = 0; |
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|
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/* CPU number: */ |
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|
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/* TODO */ |
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|
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/* Register names: */ |
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for (i=0; i<N_ARM_REGS; i++) { |
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if (strcasecmp(name, arm_regname[i]) == 0) { |
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if (writeflag) { |
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m->cpus[cpunr]->cd.arm.r[i] = *valuep; |
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if (i == ARM_PC) |
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m->cpus[cpunr]->pc = *valuep; |
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} else |
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*valuep = m->cpus[cpunr]->cd.arm.r[i]; |
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*match_register = 1; |
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} |
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} |
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} |
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|
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|
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/* |
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* arm_cpu_register_dump(): |
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* |
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* Dump cpu registers in a relatively readable format. |
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* |
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* gprs: set to non-zero to dump GPRs and some special-purpose registers. |
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* coprocs: set bit 0..3 to dump registers in coproc 0..3. |
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*/ |
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void arm_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs) |
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{ |
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char *symbol; |
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uint64_t offset; |
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int mode = cpu->cd.arm.flags & ARM_FLAG_MODE; |
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int i, x = cpu->cpu_id; |
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|
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if (gprs) { |
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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cpu->cd.arm.r[ARM_PC], &offset); |
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debug("cpu%i: flags = ", x); |
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debug("%s%s%s%s%s%s", |
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(cpu->cd.arm.flags & ARM_FLAG_N)? "N" : "n", |
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(cpu->cd.arm.flags & ARM_FLAG_Z)? "Z" : "z", |
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(cpu->cd.arm.flags & ARM_FLAG_C)? "C" : "c", |
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(cpu->cd.arm.flags & ARM_FLAG_V)? "V" : "v", |
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(cpu->cd.arm.flags & ARM_FLAG_I)? "I" : "i", |
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(cpu->cd.arm.flags & ARM_FLAG_F)? "F" : "f"); |
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if (mode < ARM_MODE_USR32) |
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debug(" pc = 0x%07x", |
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(int)(cpu->cd.arm.r[ARM_PC] & 0x03ffffff)); |
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else |
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debug(" pc = 0x%08x", (int)cpu->cd.arm.r[ARM_PC]); |
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|
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/* TODO: Flags */ |
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|
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debug(" <%s>\n", symbol != NULL? symbol : " no symbol "); |
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|
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for (i=0; i<N_ARM_REGS; i++) { |
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if ((i % 4) == 0) |
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debug("cpu%i:", x); |
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if (i != ARM_PC) |
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debug(" %s = 0x%08x", arm_regname[i], |
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(int)cpu->cd.arm.r[i]); |
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if ((i % 4) == 3) |
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debug("\n"); |
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} |
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} |
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} |
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|
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|
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/* |
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* arm_cpu_show_full_statistics(): |
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* |
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* Show detailed statistics on opcode usage on each cpu. |
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*/ |
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void arm_cpu_show_full_statistics(struct machine *m) |
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{ |
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fatal("arm_cpu_show_full_statistics(): TODO\n"); |
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} |
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|
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|
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/* |
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* arm_cpu_tlbdump(): |
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* |
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* Called from the debugger to dump the TLB in a readable format. |
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* x is the cpu number to dump, or -1 to dump all CPUs. |
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* |
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* If rawflag is nonzero, then the TLB contents isn't formated nicely, |
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* just dumped. |
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*/ |
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void arm_cpu_tlbdump(struct machine *m, int x, int rawflag) |
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{ |
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fatal("arm_cpu_tlbdump(): TODO\n"); |
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} |
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|
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|
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/* |
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* arm_cpu_interrupt(): |
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*/ |
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int arm_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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fatal("arm_cpu_interrupt(): TODO\n"); |
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return 0; |
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} |
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|
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|
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/* |
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* arm_cpu_interrupt_ack(): |
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*/ |
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int arm_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr) |
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{ |
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/* fatal("arm_cpu_interrupt_ack(): TODO\n"); */ |
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return 0; |
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} |
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|
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|
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/* |
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* arm_cpu_disassemble_instr(): |
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* |
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* Convert an instruction word into human readable format, for instruction |
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* tracing. |
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* |
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* If running is 1, cpu->pc should be the address of the instruction. |
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* |
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* If running is 0, things that depend on the runtime environment (eg. |
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* register contents) will not be shown, and addr will be used instead of |
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* cpu->pc for relative addresses. |
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*/ |
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int arm_cpu_disassemble_instr(struct cpu *cpu, unsigned char *ib, |
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int running, uint64_t dumpaddr, int bintrans) |
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{ |
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uint32_t iw, tmp; |
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int main_opcode, secondary_opcode, s_bit, r16, r12, r8; |
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int i, n, p_bit, u_bit, b_bit, w_bit, l_bit; |
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char *symbol, *condition; |
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uint64_t offset; |
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|
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if (running) |
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dumpaddr = cpu->pc; |
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|
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symbol = get_symbol_name(&cpu->machine->symbol_context, |
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dumpaddr, &offset); |
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if (symbol != NULL && offset == 0) |
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debug("<%s>\n", symbol); |
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|
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if (cpu->machine->ncpus > 1 && running) |
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debug("cpu%i:\t", cpu->cpu_id); |
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|
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debug("%08x: ", (int)dumpaddr); |
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|
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if (cpu->byte_order == EMUL_LITTLE_ENDIAN) |
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iw = ib[0] + (ib[1]<<8) + (ib[2]<<16) + (ib[3]<<24); |
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else |
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iw = ib[3] + (ib[2]<<8) + (ib[1]<<16) + (ib[0]<<24); |
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debug("%08x\t", (int)iw); |
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|
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condition = arm_condition_string[iw >> 28]; |
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main_opcode = (iw >> 24) & 15; |
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secondary_opcode = (iw >> 21) & 15; |
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u_bit = (iw >> 23) & 1; |
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b_bit = (iw >> 22) & 1; |
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w_bit = (iw >> 21) & 1; |
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s_bit = l_bit = (iw >> 20) & 1; |
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r16 = (iw >> 16) & 15; |
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r12 = (iw >> 12) & 15; |
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r8 = (iw >> 8) & 15; |
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|
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switch (main_opcode) { |
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case 0x0: |
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case 0x1: |
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case 0x2: |
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case 0x3: |
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/* |
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* See (1): |
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* xxxx000a aaaSnnnn ddddcccc ctttmmmm Register form |
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* xxxx001a aaaSnnnn ddddrrrr bbbbbbbb Immediate form |
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*/ |
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if (iw & 0x80 && !(main_opcode & 2) && iw & 0x10) { |
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debug("UNIMPLEMENTED reg (c!=0), t odd\n"); |
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break; |
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} |
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|
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debug("%s%s%s\t", arm_dpiname[secondary_opcode], |
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condition, s_bit? "s" : ""); |
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if (arm_dpi_uses_d[secondary_opcode]) |
| 330 |
debug("%s,", arm_regname[r12]); |
| 331 |
if (arm_dpi_uses_n[secondary_opcode]) |
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debug("%s,", arm_regname[r16]); |
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|
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if (main_opcode & 2) { |
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/* Immediate form: */ |
| 336 |
int r = (iw >> 7) & 30; |
| 337 |
uint32_t b = iw & 0xff; |
| 338 |
while (r-- > 0) |
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b = (b >> 1) | ((b & 1) << 31); |
| 340 |
if (b < 15) |
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debug("#%i", b); |
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else |
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debug("#0x%x", b); |
| 344 |
} else { |
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/* Register form: */ |
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int t = (iw >> 4) & 7; |
| 347 |
int c = (iw >> 7) & 31; |
| 348 |
debug("%s", arm_regname[iw & 15]); |
| 349 |
switch (t) { |
| 350 |
case 0: if (c != 0) |
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debug(", lsl #%i", c); |
| 352 |
break; |
| 353 |
case 1: debug(", lsl %s", arm_regname[c >> 1]); |
| 354 |
break; |
| 355 |
case 2: debug(", lsr #%i", c? c : 32); |
| 356 |
break; |
| 357 |
case 3: debug(", lsr %s", arm_regname[c >> 1]); |
| 358 |
break; |
| 359 |
case 4: debug(", asr #%i", c? c : 32); |
| 360 |
break; |
| 361 |
case 5: debug(", asr %s", arm_regname[c >> 1]); |
| 362 |
break; |
| 363 |
case 6: if (c != 0) |
| 364 |
debug(", ror #%i", c); |
| 365 |
else |
| 366 |
debug(", rrx"); |
| 367 |
break; |
| 368 |
case 7: debug(", ror %s", arm_regname[c >> 1]); |
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break; |
| 370 |
} |
| 371 |
} |
| 372 |
debug("\n"); |
| 373 |
break; |
| 374 |
case 0x4: /* Single Data Transfer */ |
| 375 |
case 0x5: |
| 376 |
case 0x6: |
| 377 |
case 0x7: |
| 378 |
/* |
| 379 |
* See (1): |
| 380 |
* xxxx010P UBWLnnnn ddddoooo oooooooo Immediate form |
| 381 |
* xxxx011P UBWLnnnn ddddcccc ctt0mmmm Register form |
| 382 |
*/ |
| 383 |
p_bit = main_opcode & 1; |
| 384 |
if (main_opcode >= 6 && iw & 0x10) { |
| 385 |
debug("TODO: single data transf. but 0x10\n"); |
| 386 |
break; |
| 387 |
} |
| 388 |
debug("%s%s%s", l_bit? "ldr" : "str", |
| 389 |
condition, b_bit? "b" : ""); |
| 390 |
if (!p_bit && w_bit) |
| 391 |
debug("t"); |
| 392 |
debug("\t%s,[%s", arm_regname[r12], arm_regname[r16]); |
| 393 |
if (main_opcode < 6) { |
| 394 |
/* Immediate form: */ |
| 395 |
uint32_t imm = iw & 0xfff; |
| 396 |
if (!p_bit) |
| 397 |
debug("]"); |
| 398 |
if (imm != 0) |
| 399 |
debug(",#%s%i", u_bit? "" : "-", imm); |
| 400 |
if (p_bit) |
| 401 |
debug("]"); |
| 402 |
} else { |
| 403 |
debug(" TODO: REG-form]"); |
| 404 |
} |
| 405 |
debug("%s\n", (p_bit && w_bit)? "!" : ""); |
| 406 |
break; |
| 407 |
case 0x8: /* Block Data Transfer */ |
| 408 |
case 0x9: |
| 409 |
/* See (1): xxxx100P USWLnnnn llllllll llllllll */ |
| 410 |
p_bit = main_opcode & 1; |
| 411 |
s_bit = b_bit; |
| 412 |
debug("%s%s", l_bit? "ldm" : "stm", condition); |
| 413 |
switch (u_bit * 2 + p_bit) { |
| 414 |
case 0: debug("da"); break; |
| 415 |
case 1: debug("db"); break; |
| 416 |
case 2: debug("ia"); break; |
| 417 |
case 3: debug("ib"); break; |
| 418 |
} |
| 419 |
debug("\t%s", arm_regname[r16]); |
| 420 |
if (w_bit) |
| 421 |
debug("!"); |
| 422 |
debug(",{"); |
| 423 |
n = 0; |
| 424 |
for (i=0; i<16; i++) |
| 425 |
if ((iw >> i) & 1) { |
| 426 |
debug("%s%s", (n > 0)? ",":"", arm_regname[i]); |
| 427 |
n++; |
| 428 |
} |
| 429 |
debug("}"); |
| 430 |
if (s_bit) |
| 431 |
debug("^"); |
| 432 |
debug("\n"); |
| 433 |
break; |
| 434 |
case 0xa: /* B: branch */ |
| 435 |
case 0xb: /* BL: branch and link */ |
| 436 |
debug("b%s%s\t", main_opcode == 0xa? "" : "l", condition); |
| 437 |
tmp = (iw & 0x00ffffff) << 2; |
| 438 |
if (tmp & 0x02000000) |
| 439 |
tmp |= 0xfc000000; |
| 440 |
tmp = (int32_t)(dumpaddr + tmp + 8); |
| 441 |
debug("0x%x", (int)tmp); |
| 442 |
symbol = get_symbol_name(&cpu->machine->symbol_context, |
| 443 |
tmp, &offset); |
| 444 |
if (symbol != NULL) |
| 445 |
debug("\t\t<%s>", symbol); |
| 446 |
debug("\n"); |
| 447 |
break; |
| 448 |
case 0xc: /* Coprocessor */ |
| 449 |
case 0xd: /* LDC/STC */ |
| 450 |
/* xxxx110P UNWLnnnn DDDDpppp oooooooo LDC/STC */ |
| 451 |
debug("TODO: coprocessor LDC/STC\n"); |
| 452 |
break; |
| 453 |
case 0xe: /* CDP (Coprocessor Op) */ |
| 454 |
/* or MRC/MCR! |
| 455 |
* According to (1): |
| 456 |
* xxxx1110 oooonnnn ddddpppp qqq0mmmm CDP |
| 457 |
* xxxx1110 oooLNNNN ddddpppp qqq1MMMM MRC/MCR |
| 458 |
*/ |
| 459 |
if (iw & 0x10) { |
| 460 |
debug("%s%s\t", |
| 461 |
(iw & 0x00100000)? "mrc" : "mcr", condition); |
| 462 |
debug("%i,%i,r%i,cr%i,cr%i,%i", |
| 463 |
(int)((iw >> 8) & 15), (int)((iw >>21) & 7), |
| 464 |
(int)((iw >>12) & 15), (int)((iw >>16) & 15), |
| 465 |
(int)((iw >> 0) & 15), (int)((iw >> 5) & 7)); |
| 466 |
} else { |
| 467 |
debug("cdp%s\t", condition); |
| 468 |
debug("%i,%i,cr%i,cr%i,cr%i", |
| 469 |
(int)((iw >> 8) & 15), |
| 470 |
(int)((iw >>20) & 15), |
| 471 |
(int)((iw >>12) & 15), |
| 472 |
(int)((iw >>16) & 15), |
| 473 |
(int)((iw >> 0) & 15)); |
| 474 |
if ((iw >> 5) & 7) |
| 475 |
debug(",0x%x", (int)((iw >> 5) & 7)); |
| 476 |
} |
| 477 |
debug("\n"); |
| 478 |
break; |
| 479 |
case 0xf: /* SWI */ |
| 480 |
debug("swi%s\t", condition); |
| 481 |
debug("0x%x\n", (int)(iw & 0x00ffffff)); |
| 482 |
break; |
| 483 |
default:debug("UNIMPLEMENTED\n"); |
| 484 |
} |
| 485 |
|
| 486 |
return sizeof(uint32_t); |
| 487 |
} |
| 488 |
|
| 489 |
|
| 490 |
#include "tmp_arm_tail.c" |
| 491 |
|
| 492 |
|
| 493 |
#endif /* ENABLE_ARM */ |
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