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/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_dec_ioasic.c,v 1.12 2005/02/22 20:18:30 debug Exp $ |
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* |
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* DECstation "3MIN" and "3MAX" IOASIC device. |
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* |
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* TODO: Lots of stuff, such as DMA and all bits in the control registers. |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "devices.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "dec_kn03.h" |
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#include "tc_ioasicreg.h" |
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|
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#define IOASIC_DEBUG |
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/* #define debug fatal */ |
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|
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/* |
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* dev_dec_ioasic_access(): |
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*/ |
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int dev_dec_ioasic_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct dec_ioasic_data *d = (struct dec_ioasic_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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uint64_t curptr; |
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int dma_len, dma_res; |
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uint32_t csr; |
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int regnr; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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regnr = (relative_addr - IOASIC_SLOT_1_START) / 0x10; |
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if (relative_addr < 0x80000 && (relative_addr & 0xf) != 0) |
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fatal("[ dec_ioasic: unaligned access? relative_addr = " |
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"0x%x ]\n", (int)relative_addr); |
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|
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if (regnr >= 0 && regnr < N_DEC_IOASIC_REGS) { |
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if (writeflag == MEM_WRITE) |
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d->reg[regnr] = idata; |
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else |
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odata = d->reg[regnr]; |
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} |
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|
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#ifdef IOASIC_DEBUG |
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if (writeflag == MEM_WRITE) |
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debug("[ dec_ioasic: write to address 0x%llx, data=0x" |
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"%016llx ]\n", (long long)relative_addr, (long long)idata); |
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else |
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debug("[ dec_ioasic: read from address 0x%llx ]\n", |
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(long long)relative_addr); |
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#endif |
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|
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switch (relative_addr) { |
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|
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/* Don't print warnings for these: */ |
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case IOASIC_SCSI_DMAPTR: |
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case IOASIC_SCC_T1_DMAPTR: |
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case IOASIC_SCC_T2_DMAPTR: |
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case IOASIC_SCC_R1_DMAPTR: |
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case IOASIC_SCC_R2_DMAPTR: |
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break; |
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|
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case IOASIC_CSR: |
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if (writeflag == MEM_WRITE) { |
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csr = d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / 0x10]; |
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|
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d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &= |
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~IOASIC_INTR_T2_PAGE_END; |
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|
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if (csr & IOASIC_CSR_DMAEN_T2) { |
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/* Transmit data: */ |
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curptr = (d->reg[(IOASIC_SCC_T2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] >> 3) |
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| ((d->reg[(IOASIC_SCC_T2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29); |
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dma_len = 0x1000 - (curptr & 0xffc); |
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|
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if ((curptr & 0xfff) == 0) |
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break; |
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|
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if (d->dma_func[3] != NULL) { |
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d->dma_func[3](cpu, |
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d->dma_func_extra[3], curptr, |
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dma_len, 1); |
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} else |
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fatal("[ dec_ioasic: DMA tx: data @ " |
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"%08x, len %i bytes, but no " |
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"handler? ]\n", (int)curptr, |
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dma_len); |
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|
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/* and signal the end of page: */ |
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d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / |
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0x10] |= IOASIC_INTR_T2_PAGE_END; |
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|
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d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START) / |
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0x10] &= ~IOASIC_CSR_DMAEN_T2; |
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curptr |= 0xfff; |
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curptr ++; |
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|
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d->reg[(IOASIC_SCC_T2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] = ((curptr << |
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3) & ~0x1f) | ((curptr >> 29) & 0x1f); |
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} |
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|
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if (csr & IOASIC_CSR_DMAEN_R2) { |
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/* Receive data: */ |
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curptr = (d->reg[(IOASIC_SCC_R2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] >> 3) |
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| ((d->reg[(IOASIC_SCC_R2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] & 0x1f) << 29); |
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dma_len = 0x1000 - (curptr & 0xffc); |
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|
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dma_res = 0; |
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if (d->dma_func[3] != NULL) { |
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dma_res = d->dma_func[3](cpu, |
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d->dma_func_extra[3], curptr, |
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dma_len, 0); |
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} else |
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fatal("[ dec_ioasic: DMA tx: data @ " |
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"%08x, len %i bytes, but no " |
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"handler? ]\n", (int)curptr, |
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dma_len); |
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|
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/* and signal the end of page: */ |
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if (dma_res > 0) { |
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if ((curptr & 0x800) != ((curptr + |
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dma_res) & 0x800)) |
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d->reg[(IOASIC_INTR - |
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IOASIC_SLOT_1_START) / 0x10] |
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|= IOASIC_INTR_R2_HALF_PAGE; |
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curptr += dma_res; |
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/* d->reg[(IOASIC_CSR - IOASIC_SLOT_1_START |
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) / 0x10] &= ~IOASIC_CSR_DMAEN_R2; */ |
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d->reg[(IOASIC_SCC_R2_DMAPTR - |
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IOASIC_SLOT_1_START) / 0x10] = |
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((curptr << 3) & ~0x1f) | ((curptr |
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>> 29) & 0x1f); |
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} |
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} |
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} |
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break; |
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|
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case IOASIC_INTR: |
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if (writeflag == MEM_READ) { |
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odata = d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) |
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/ 0x10]; |
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/* Note/TODO: How about other models than KN03? */ |
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if (!d->rackmount_flag) |
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odata |= KN03_INTR_PROD_JUMPER; |
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} else { |
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/* Clear bits on write. */ |
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d->reg[(IOASIC_INTR - IOASIC_SLOT_1_START) / 0x10] &= |
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~idata; |
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|
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/* Make sure that the CPU interrupt is deasserted as |
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well: */ |
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if (idata != 0) |
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cpu_interrupt_ack(cpu, 8 + idata); |
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} |
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break; |
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|
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case IOASIC_IMSK: |
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if (writeflag == MEM_WRITE) { |
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d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / 0x10] = |
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idata; |
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cpu_interrupt_ack(cpu, 8 + 0); |
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} else |
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odata = d->reg[(IOASIC_IMSK - IOASIC_SLOT_1_START) / |
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0x10]; |
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break; |
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|
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case IOASIC_CTR: |
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if (writeflag == MEM_READ) |
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odata = 0; |
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break; |
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|
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case 0x80000: |
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case 0x80004: |
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case 0x80008: |
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case 0x8000c: |
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case 0x80010: |
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case 0x80014: |
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/* Station's ethernet address: */ |
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if (writeflag == MEM_WRITE) { |
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fatal("[ dec_ioasic: attempt to write to the station's" |
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" ethernet address? ]\n"); |
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} else { |
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odata = ((relative_addr - 0x80000) / 4 + 1) * 0x10; |
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} |
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break; |
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|
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default: |
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if (writeflag == MEM_WRITE) |
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fatal("[ dec_ioasic: unimplemented write to address " |
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"0x%llx, data=0x%016llx ]\n", |
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(long long)relative_addr, (long long)idata); |
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else |
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fatal("[ dec_ioasic: unimplemented read from address " |
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"0x%llx ]\n", (long long)relative_addr); |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_dec_ioasic_init(): |
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* |
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* For DECstation "type 4", the rackmount_flag selects which model type |
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* the IOASIC should identify itself as (5000 for zero, 5900 if rackmount_flag |
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* is non-zero). It is probably not meaningful on other machines than |
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* type 4. |
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*/ |
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struct dec_ioasic_data *dev_dec_ioasic_init(struct cpu *cpu, |
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struct memory *mem, uint64_t baseaddr, int rackmount_flag) |
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{ |
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struct dec_ioasic_data *d = malloc(sizeof(struct dec_ioasic_data)); |
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct dec_ioasic_data)); |
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|
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d->rackmount_flag = rackmount_flag; |
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|
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memory_device_register(mem, "dec_ioasic", baseaddr, |
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DEV_DEC_IOASIC_LENGTH, dev_dec_ioasic_access, (void *)d, |
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MEM_DEFAULT, NULL); |
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return d; |
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} |
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