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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_8259.c,v 1.9 2005/06/02 17:11:35 debug Exp $ |
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* |
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* 8259 Programmable Interrupt Controller. |
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* |
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* This is mostly bogus. TODO. See the following URL for more details: |
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* http://www.nondot.org/sabre/os/files/MiscHW/8259pic.txt |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "cpu.h" |
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#include "device.h" |
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#include "devices.h" |
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#include "emul.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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|
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#define DEV_8259_LENGTH 2 |
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|
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|
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/* |
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* dev_8259_access(): |
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*/ |
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int dev_8259_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct pic8259_data *d = (struct pic8259_data *) extra; |
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uint64_t idata = 0, odata = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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case 0x00: |
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if (writeflag == MEM_WRITE) { |
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if ((idata & 0x10) == 0x10) { |
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/* Bit 3: 0=edge, 1=level */ |
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if (idata & 0x08) |
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fatal("[ 8259: TODO: Level " |
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"triggered (MCA bus) ]\n"); |
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if (idata & 0x04) |
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fatal("[ 8259: WARNING: Bit 2 set ]\n"); |
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/* Bit 1: 0=cascade, 1=single */ |
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/* Bit 0: 1=4th init byte */ |
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if (!(idata & 0x01)) |
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fatal("[ 8259: WARNING: Bit 0 NOT set!" |
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"!! ]\n"); |
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d->init_state = 1; |
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break; |
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} |
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|
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/* TODO: Is it ok to abort init state when there |
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is a non-init command? */ |
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if (d->init_state) |
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fatal("[ 8259: WARNING: Was in init-state, but" |
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" it was aborted? ]\n"); |
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d->init_state = 0; |
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|
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switch (idata) { |
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case 0x0a: |
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d->current_command = 0x0a; |
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break; |
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case 0x0b: |
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d->current_command = 0x0b; |
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break; |
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case 0x20: /* End Of Interrupt */ |
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d->irr &= ~d->isr; |
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d->isr = 0; |
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/* Recalculate interrupt assertions: */ |
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cpu_interrupt(cpu, 16); |
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break; |
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case 0x60: |
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case 0x61: |
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case 0x62: |
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case 0x63: |
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case 0x64: |
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case 0x65: |
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case 0x66: |
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case 0x67: /* Specific EOI */ |
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d->irr &= ~(1 << (idata & 7)); |
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d->isr &= ~(1 << (idata & 7)); |
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/* Recalculate interrupt assertions: */ |
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cpu_interrupt(cpu, 16); |
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break; |
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case 0x68: /* Set Special Mask Mode */ |
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/* TODO */ |
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break; |
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case 0xc0: |
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case 0xc1: |
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case 0xc2: |
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case 0xc3: |
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case 0xc4: |
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case 0xc5: |
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case 0xc6: |
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case 0xc7: /* Set IRQ Priority Order */ |
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/* TODO */ |
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break; |
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default: |
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fatal("[ 8259: unimplemented command 0x%02x" |
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" ]\n", idata); |
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cpu->running = 0; |
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} |
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} else { |
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switch (d->current_command) { |
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case 0x0a: |
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odata = d->irr; |
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break; |
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case 0x0b: |
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odata = d->isr; |
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break; |
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default: |
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fatal("[ 8259: unimplemented command 0x%02x" |
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" while reading ]\n", d->current_command); |
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cpu->running = 0; |
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} |
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} |
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break; |
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case 0x01: |
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if (d->init_state > 0) { |
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if (d->init_state == 1) { |
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d->irq_base = idata & 0xf8; |
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if (idata & 7) |
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fatal("[ 8259: WARNING! Lowest" |
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" bits in Init Cmd 1 are" |
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" non-zero! ]\n"); |
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d->init_state = 2; |
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} else if (d->init_state == 2) { |
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/* Slave attachment. TODO */ |
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d->init_state = 3; |
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} else if (d->init_state == 3) { |
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if (idata & 0x02) |
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fatal("[ 8259: WARNING! Bit 1 i" |
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"n Init Cmd 4 is set! ]\n"); |
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if (!(idata & 0x01)) |
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fatal("[ 8259: WARNING! Bit 0 " |
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"in Init Cmd 4 is not" |
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" set! ]\n"); |
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d->init_state = 0; |
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} |
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break; |
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} |
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|
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if (writeflag == MEM_WRITE) { |
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d->ier = idata; |
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/* Recalculate interrupt assertions: */ |
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cpu_interrupt(cpu, 16); |
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} else { |
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odata = d->ier; |
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} |
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break; |
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default: |
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if (writeflag == MEM_WRITE) { |
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fatal("[ 8259: unimplemented write to address 0x%x" |
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" data=0x%02x ]\n", (int)relative_addr, (int)idata); |
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cpu->running = 0; |
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} else { |
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fatal("[ 8259: unimplemented read from address 0x%x " |
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"]\n", (int)relative_addr); |
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cpu->running = 0; |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* devinit_8259(): |
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*/ |
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int devinit_8259(struct devinit *devinit) |
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{ |
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struct pic8259_data *d = malloc(sizeof(struct pic8259_data)); |
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char *name2; |
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int nlen = 40; |
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|
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if (d == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d, 0, sizeof(struct pic8259_data)); |
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d->irq_nr = devinit->irq_nr; |
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|
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name2 = malloc(nlen); |
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snprintf(name2, nlen, "%s", devinit->name); |
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if ((devinit->addr & 0xfff) == 0xa0) |
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strcat(name2, " [secondary]"); |
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|
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memory_device_register(devinit->machine->memory, name2, |
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devinit->addr, DEV_8259_LENGTH, dev_8259_access, (void *)d, |
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MEM_DEFAULT, NULL); |
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|
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devinit->return_ptr = d; |
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return 1; |
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} |
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