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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: memory_rw.c,v 1.10 2005/03/01 08:23:55 debug Exp $ |
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* |
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* Generic memory_rw(), with special hacks for specific CPU families. |
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* |
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* Example for inclusion from memory_mips.c: |
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* |
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* MEMORY_RW should be mips_memory_rw |
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* MEM_MIPS should be defined |
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*/ |
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|
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|
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/* |
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* memory_rw(): |
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* |
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* Read or write data from/to memory. |
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* |
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* cpu the cpu doing the read/write |
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* mem the memory object to use |
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* vaddr the virtual address |
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* data a pointer to the data to be written to memory, or |
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* a placeholder for data when reading from memory |
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* len the length of the 'data' buffer |
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* writeflag set to MEM_READ or MEM_WRITE |
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* cache_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
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* |
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* If the address indicates access to a memory mapped device, that device' |
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* read/write access function is called. |
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* |
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* If instruction latency/delay support is enabled, then |
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* cpu->instruction_delay is increased by the number of instruction to |
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* delay execution. |
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* |
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* This function should not be called with cpu == NULL. |
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* |
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* Returns one of the following: |
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* MEMORY_ACCESS_FAILED |
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* MEMORY_ACCESS_OK |
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* |
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* (MEMORY_ACCESS_FAILED is 0.) |
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*/ |
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int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags) |
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{ |
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#ifndef MEM_USERLAND |
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int ok = 1; |
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#endif |
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uint64_t paddr; |
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int cache, no_exceptions, offset; |
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unsigned char *memblock; |
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#ifdef BINTRANS |
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int bintrans_cached = cpu->machine->bintrans_enable; |
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#endif |
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no_exceptions = cache_flags & NO_EXCEPTIONS; |
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cache = cache_flags & CACHE_FLAGS_MASK; |
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|
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#ifdef MEM_PPC |
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if (cpu->cd.ppc.bits == 32) |
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vaddr &= 0xffffffff; |
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#endif |
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|
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#ifdef MEM_URISC |
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{ |
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uint64_t mask = (uint64_t) -1; |
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if (cpu->cd.urisc.wordlen < 64) |
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mask = ((int64_t)1 << cpu->cd.urisc.wordlen) - 1; |
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vaddr &= mask; |
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} |
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#endif |
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|
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#ifdef MEM_MIPS |
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#ifdef BINTRANS |
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if (bintrans_cached) { |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_host_4kpage = NULL; |
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cpu->cd.mips.pc_bintrans_paddr_valid = 0; |
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} |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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|
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#ifdef MEM_USERLAND |
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paddr = vaddr & 0x7fffffff; |
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goto have_paddr; |
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#endif |
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|
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#ifndef MEM_USERLAND |
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#ifdef MEM_MIPS |
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/* |
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* For instruction fetch, are we on the same page as the last |
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* instruction we fetched? |
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* |
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* NOTE: There's no need to check this stuff here if this address |
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* is known to be in host ram, as it's done at instruction fetch |
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* time in cpu.c! Only check if _host_4k_page == NULL. |
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*/ |
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if (cache == CACHE_INSTRUCTION && |
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cpu->cd.mips.pc_last_host_4k_page == NULL && |
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(vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) { |
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paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff); |
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goto have_paddr; |
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} |
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#endif /* MEM_MIPS */ |
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|
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if (cache_flags & PHYSICAL || cpu->translate_address == NULL) { |
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paddr = vaddr; |
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} else { |
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ok = cpu->translate_address(cpu, vaddr, &paddr, |
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(writeflag? FLAG_WRITEFLAG : 0) + |
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(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
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+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
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/* If the translation caused an exception, or was invalid in |
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some way, we simply return without doing the memory |
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access: */ |
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if (!ok) |
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return MEMORY_ACCESS_FAILED; |
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} |
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|
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|
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#ifdef MEM_MIPS |
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/* |
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* If correct cache emulation is enabled, and we need to simluate |
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* cache misses even from the instruction cache, we can't run directly |
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* from a host page. :-/ |
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*/ |
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#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS) |
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#else |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff; |
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cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff; |
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cpu->cd.mips.pc_last_host_4k_page = NULL; |
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|
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/* _last_host_4k_page will be set to 1 further down, |
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if the page is actually in host ram */ |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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#endif /* ifndef MEM_USERLAND */ |
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|
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|
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have_paddr: |
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|
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|
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#ifdef MEM_MIPS |
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/* TODO: How about bintrans vs cache emulation? */ |
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#ifdef BINTRANS |
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if (bintrans_cached) { |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_paddr_valid = 1; |
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cpu->cd.mips.pc_bintrans_paddr = paddr; |
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} |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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|
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|
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if (!(cache_flags & PHYSICAL)) |
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if (no_exceptions) |
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goto no_exception_access; |
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|
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|
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#ifndef MEM_USERLAND |
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/* |
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* Memory mapped device? |
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* |
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* TODO: this is utterly slow. |
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* TODO2: if paddr<base, but len enough, then we should write |
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* to a device to |
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*/ |
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if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
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#ifdef BINTRANS |
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uint64_t orig_paddr = paddr; |
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#endif |
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int i, start, res; |
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i = start = mem->last_accessed_device; |
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|
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/* Scan through all devices: */ |
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do { |
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if (paddr >= mem->dev_baseaddr[i] && |
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paddr < mem->dev_baseaddr[i] + mem->dev_length[i]) { |
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/* Found a device, let's access it: */ |
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mem->last_accessed_device = i; |
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|
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paddr -= mem->dev_baseaddr[i]; |
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if (paddr + len > mem->dev_length[i]) |
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len = mem->dev_length[i] - paddr; |
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|
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#ifdef BINTRANS |
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if (bintrans_cached && mem->dev_flags[i] & |
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MEM_BINTRANS_OK) { |
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int wf = writeflag == MEM_WRITE? 1 : 0; |
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|
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if (writeflag) { |
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if (paddr < mem-> |
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dev_bintrans_write_low[i]) |
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mem-> |
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dev_bintrans_write_low |
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[i] = |
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paddr & ~0xfff; |
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if (paddr > mem-> |
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dev_bintrans_write_high[i]) |
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mem-> |
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dev_bintrans_write_high |
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[i] = paddr | 0xfff; |
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} |
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|
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if (!(mem->dev_flags[i] & |
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MEM_BINTRANS_WRITE_OK)) |
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wf = 0; |
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|
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update_translation_table(cpu, |
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vaddr & ~0xfff, |
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mem->dev_bintrans_data[i] + |
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(paddr & ~0xfff), |
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wf, orig_paddr & ~0xfff); |
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} |
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#endif |
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|
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res = mem->dev_f[i](cpu, mem, paddr, data, len, |
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writeflag, mem->dev_extra[i]); |
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|
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#ifdef ENABLE_INSTRUCTION_DELAYS |
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if (res == 0) |
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res = -1; |
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|
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cpu->cd.mips.instruction_delay += |
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( (abs(res) - 1) * |
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cpu->cd.mips.cpu_type.instrs_per_cycle ); |
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#endif |
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/* |
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* If accessing the memory mapped device |
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* failed, then return with a DBE exception. |
| 259 |
*/ |
| 260 |
if (res <= 0) { |
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debug("%s device '%s' addr %08lx " |
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"failed\n", writeflag? |
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"writing to" : "reading from", |
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mem->dev_name[i], (long)paddr); |
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#ifdef MEM_MIPS |
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mips_cpu_exception(cpu, EXCEPTION_DBE, |
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0, vaddr, 0, 0, 0, 0); |
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#endif |
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return MEMORY_ACCESS_FAILED; |
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} |
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|
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goto do_return_ok; |
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} |
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|
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i ++; |
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if (i == mem->n_mmapped_devices) |
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i = 0; |
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} while (i != start); |
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} |
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|
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|
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#ifdef MEM_MIPS |
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/* |
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* Data and instruction cache emulation: |
| 285 |
*/ |
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|
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switch (cpu->cd.mips.cpu_type.mmu_model) { |
| 288 |
case MMU3K: |
| 289 |
/* if not uncached addess (TODO: generalize this) */ |
| 290 |
if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE && |
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!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
| 292 |
(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
| 293 |
if (memory_cache_R3000(cpu, cache, paddr, |
| 294 |
writeflag, len, data)) |
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goto do_return_ok; |
| 296 |
} |
| 297 |
break; |
| 298 |
#if 0 |
| 299 |
/* Remove this, it doesn't work anyway */ |
| 300 |
case MMU10K: |
| 301 |
/* other cpus: */ |
| 302 |
/* |
| 303 |
* SUPER-UGLY HACK for SGI-IP32 PROM, R10000: |
| 304 |
* K0 bits == 0x3 means uncached... |
| 305 |
* |
| 306 |
* It seems that during bootup, the SGI-IP32 prom |
| 307 |
* stores a return pointers a 0x80000f10, then tests |
| 308 |
* memory by writing bit patterns to 0xa0000xxx, and |
| 309 |
* then when it's done, reads back the return pointer |
| 310 |
* from 0x80000f10. |
| 311 |
* |
| 312 |
* I need to find the correct way to disconnect the |
| 313 |
* cache from the main memory for R10000. (TODO !!!) |
| 314 |
*/ |
| 315 |
/* if ((cpu->cd.mips.coproc[0]->reg[COP0_CONFIG] & 7) == 3) { */ |
| 316 |
/* |
| 317 |
if (cache == CACHE_DATA && |
| 318 |
cpu->r10k_cache_disable_TODO) { |
| 319 |
paddr &= ((512*1024)-1); |
| 320 |
paddr += 512*1024; |
| 321 |
} |
| 322 |
*/ |
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break; |
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#endif |
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default: |
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/* R4000 etc */ |
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/* TODO */ |
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; |
| 329 |
} |
| 330 |
#endif /* MEM_MIPS */ |
| 331 |
|
| 332 |
|
| 333 |
/* Outside of physical RAM? */ |
| 334 |
if (paddr >= mem->physical_max) { |
| 335 |
if ((paddr & 0xffff000000ULL) == 0x1f000000) { |
| 336 |
/* Ok, this is PROM stuff */ |
| 337 |
} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) { |
| 338 |
/* Sprite reads from this area of memory... */ |
| 339 |
/* TODO: is this still correct? */ |
| 340 |
if (writeflag == MEM_READ) |
| 341 |
memset(data, 0, len); |
| 342 |
goto do_return_ok; |
| 343 |
} else { |
| 344 |
if (paddr >= mem->physical_max + 0 * 1024) { |
| 345 |
char *symbol; |
| 346 |
#ifdef MEM_MIPS |
| 347 |
uint64_t offset; |
| 348 |
#endif |
| 349 |
if (!quiet_mode) { |
| 350 |
fatal("[ memory_rw(): writeflag=%i ", |
| 351 |
writeflag); |
| 352 |
if (writeflag) { |
| 353 |
unsigned int i; |
| 354 |
debug("data={", writeflag); |
| 355 |
if (len > 16) { |
| 356 |
int start2 = len-16; |
| 357 |
for (i=0; i<16; i++) |
| 358 |
debug("%s%02x", |
| 359 |
i?",":"", |
| 360 |
data[i]); |
| 361 |
debug(" .. "); |
| 362 |
if (start2 < 16) |
| 363 |
start2 = 16; |
| 364 |
for (i=start2; i<len; |
| 365 |
i++) |
| 366 |
debug("%s%02x", |
| 367 |
i?",":"", |
| 368 |
data[i]); |
| 369 |
} else |
| 370 |
for (i=0; i<len; i++) |
| 371 |
debug("%s%02x", |
| 372 |
i?",":"", |
| 373 |
data[i]); |
| 374 |
debug("}"); |
| 375 |
} |
| 376 |
#ifdef MEM_MIPS |
| 377 |
symbol = get_symbol_name( |
| 378 |
&cpu->machine->symbol_context, |
| 379 |
cpu->cd.mips.pc_last, &offset); |
| 380 |
#else |
| 381 |
symbol = "(unimpl for non-MIPS)"; |
| 382 |
#endif |
| 383 |
|
| 384 |
/* TODO: fix! not mips.pc_last for for example ppc */ |
| 385 |
|
| 386 |
fatal(" paddr=%llx >= physical_max pc=" |
| 387 |
"0x%08llx <%s> ]\n", |
| 388 |
(long long)paddr, |
| 389 |
(long long)cpu->cd.mips.pc_last, |
| 390 |
symbol? symbol : "no symbol"); |
| 391 |
} |
| 392 |
|
| 393 |
if (cpu->machine->single_step_on_bad_addr) { |
| 394 |
fatal("[ unimplemented access to " |
| 395 |
"0x%016llx, pc = 0x%016llx ]\n", |
| 396 |
(long long)paddr, |
| 397 |
(long long)cpu->pc); |
| 398 |
single_step = 1; |
| 399 |
} |
| 400 |
} |
| 401 |
|
| 402 |
if (writeflag == MEM_READ) { |
| 403 |
/* Return all zeroes? (Or 0xff? TODO) */ |
| 404 |
memset(data, 0, len); |
| 405 |
|
| 406 |
#ifdef MEM_MIPS |
| 407 |
/* |
| 408 |
* For real data/instruction accesses, cause |
| 409 |
* an exceptions on an illegal read: |
| 410 |
*/ |
| 411 |
if (cache != CACHE_NONE && cpu->machine-> |
| 412 |
dbe_on_nonexistant_memaccess) { |
| 413 |
if (paddr >= mem->physical_max && |
| 414 |
paddr < mem->physical_max+1048576) |
| 415 |
mips_cpu_exception(cpu, |
| 416 |
EXCEPTION_DBE, 0, vaddr, 0, |
| 417 |
0, 0, 0); |
| 418 |
} |
| 419 |
#endif /* MEM_MIPS */ |
| 420 |
} |
| 421 |
|
| 422 |
/* Hm? Shouldn't there be a DBE exception for |
| 423 |
invalid writes as well? TODO */ |
| 424 |
|
| 425 |
goto do_return_ok; |
| 426 |
} |
| 427 |
} |
| 428 |
|
| 429 |
#endif /* ifndef MEM_USERLAND */ |
| 430 |
|
| 431 |
|
| 432 |
no_exception_access: |
| 433 |
|
| 434 |
/* |
| 435 |
* Uncached access: |
| 436 |
*/ |
| 437 |
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
| 438 |
if (memblock == NULL) { |
| 439 |
if (writeflag == MEM_READ) |
| 440 |
memset(data, 0, len); |
| 441 |
goto do_return_ok; |
| 442 |
} |
| 443 |
|
| 444 |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
| 445 |
|
| 446 |
#ifdef BINTRANS |
| 447 |
if (bintrans_cached) |
| 448 |
update_translation_table(cpu, vaddr & ~0xfff, |
| 449 |
memblock + (offset & ~0xfff), |
| 450 |
#if 0 |
| 451 |
cache == CACHE_INSTRUCTION? |
| 452 |
(writeflag == MEM_WRITE? 1 : 0) |
| 453 |
: ok - 1, |
| 454 |
#else |
| 455 |
writeflag == MEM_WRITE? 1 : 0, |
| 456 |
#endif |
| 457 |
paddr & ~0xfff); |
| 458 |
#endif |
| 459 |
|
| 460 |
if (writeflag == MEM_WRITE) { |
| 461 |
if (len == sizeof(uint32_t) && (offset & 3)==0) |
| 462 |
*(uint32_t *)(memblock + offset) = *(uint32_t *)data; |
| 463 |
else if (len == sizeof(uint8_t)) |
| 464 |
*(uint8_t *)(memblock + offset) = *(uint8_t *)data; |
| 465 |
else |
| 466 |
memcpy(memblock + offset, data, len); |
| 467 |
} else { |
| 468 |
if (len == sizeof(uint32_t) && (offset & 3)==0) |
| 469 |
*(uint32_t *)data = *(uint32_t *)(memblock + offset); |
| 470 |
else if (len == sizeof(uint8_t)) |
| 471 |
*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
| 472 |
else |
| 473 |
memcpy(data, memblock + offset, len); |
| 474 |
|
| 475 |
if (cache == CACHE_INSTRUCTION) { |
| 476 |
cpu->cd.mips.pc_last_host_4k_page = memblock |
| 477 |
+ (offset & ~0xfff); |
| 478 |
#ifdef BINTRANS |
| 479 |
if (bintrans_cached) { |
| 480 |
cpu->cd.mips.pc_bintrans_host_4kpage = |
| 481 |
cpu->cd.mips.pc_last_host_4k_page; |
| 482 |
} |
| 483 |
#endif |
| 484 |
} |
| 485 |
} |
| 486 |
|
| 487 |
|
| 488 |
do_return_ok: |
| 489 |
return MEMORY_ACCESS_OK; |
| 490 |
} |
| 491 |
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