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/* |
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* Copyright (C) 2004-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: dev_au1x00.c,v 1.11 2005/02/21 09:37:43 debug Exp $ |
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* |
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* Au1x00 (eg Au1500) pseudo device. See aureg.h for bitfield details. |
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* |
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* The MeshCube uses an Au1500 CPU. |
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* |
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* This is basically just a huge TODO. :-) |
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*/ |
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|
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#include <stdio.h> |
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#include <stdlib.h> |
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#include <string.h> |
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|
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#include "console.h" |
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#include "cpu.h" |
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#include "devices.h" |
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#include "machine.h" |
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#include "memory.h" |
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#include "misc.h" |
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|
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#include "aureg.h" |
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|
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|
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struct au1x00_uart_data { |
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int console_handle; |
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int uart_nr; |
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int irq_nr; |
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uint32_t int_enable; |
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uint32_t modem_control; |
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}; |
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|
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|
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struct au1x00_pc_data { |
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uint32_t reg[PC_SIZE/4 + 2]; |
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int irq_nr; |
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}; |
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|
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|
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/* |
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* dev_au1x00_ic_access(): |
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* |
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* Interrupt Controller. |
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*/ |
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int dev_au1x00_ic_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct au1x00_ic_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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/* TODO */ |
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|
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switch (relative_addr) { |
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case IC_CONFIG0_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->config0; |
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else |
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d->config0 |= idata; |
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break; |
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case IC_CONFIG0_CLEAR: |
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if (writeflag == MEM_READ) |
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odata = d->config0; |
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else |
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d->config0 &= ~idata; |
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break; |
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case IC_CONFIG1_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->config1; |
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else |
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d->config1 |= idata; |
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break; |
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case IC_CONFIG1_CLEAR: |
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if (writeflag == MEM_READ) |
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odata = d->config1; |
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else |
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d->config1 &= ~idata; |
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break; |
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case IC_CONFIG2_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->config2; |
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else |
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d->config2 |= idata; |
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break; |
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case IC_CONFIG2_CLEAR: /* or IC_REQUEST0_INT */ |
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if (writeflag == MEM_READ) |
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odata = d->request0_int; |
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else |
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d->config2 &= ~idata; |
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break; |
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case IC_SOURCE_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->source; |
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else |
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d->source |= idata; |
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break; |
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case IC_SOURCE_CLEAR: /* or IC_REQUEST1_INT */ |
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if (writeflag == MEM_READ) |
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odata = d->request1_int; |
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else |
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d->source &= ~idata; |
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break; |
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case IC_ASSIGN_REQUEST_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->assign_request; |
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else |
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d->assign_request |= idata; |
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break; |
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case IC_ASSIGN_REQUEST_CLEAR: |
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if (writeflag == MEM_READ) |
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odata = d->assign_request; |
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else |
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d->assign_request &= ~idata; |
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break; |
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case IC_WAKEUP_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->wakeup; |
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else |
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d->wakeup |= idata; |
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break; |
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case IC_WAKEUP_CLEAR: |
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if (writeflag == MEM_READ) |
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odata = d->wakeup; |
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else |
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d->wakeup &= ~idata; |
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break; |
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case IC_MASK_READ: /* READ or SET */ |
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if (writeflag == MEM_READ) |
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odata = d->mask; |
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else |
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d->mask |= idata; |
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break; |
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case IC_MASK_CLEAR: |
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if (writeflag == MEM_READ) |
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odata = d->mask; |
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else |
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d->mask &= ~idata; |
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break; |
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default: |
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if (writeflag == MEM_READ) { |
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debug("[ au1x00_ic%i: read from 0x%08lx: 0x%08x ]\n", |
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d->ic_nr, (long)relative_addr, odata); |
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} else { |
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debug("[ au1x00_ic%i: write to 0x%08lx: 0x%08x ]\n", |
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d->ic_nr, (long)relative_addr, idata); |
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} |
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} |
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|
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if (writeflag == MEM_WRITE) |
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cpu_interrupt(cpu, 8 + 64); |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_au1x00_uart_access(): |
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* |
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* UART (Serial controllers). |
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*/ |
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int dev_au1x00_uart_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct au1x00_uart_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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switch (relative_addr) { |
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case UART_RXDATA: /* 0x00 */ |
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odata = console_readchar(d->console_handle); |
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break; |
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case UART_TXDATA: /* 0x04 */ |
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console_putchar(d->console_handle, idata); |
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break; |
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case UART_INTERRUPT_ENABLE: /* 0x08 */ |
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if (writeflag == MEM_READ) |
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odata = d->int_enable; |
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else |
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d->int_enable = idata; |
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break; |
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case UART_MODEM_CONTROL: /* 0x18 */ |
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if (writeflag == MEM_READ) |
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odata = d->modem_control; |
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else |
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d->modem_control = idata; |
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break; |
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case UART_LINE_STATUS: /* 0x1c */ |
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odata = ULS_TE + ULS_TFE; |
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if (console_charavail(d->console_handle)) |
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odata |= ULS_DR; |
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break; |
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case UART_CLOCK_DIVIDER: /* 0x28 */ |
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break; |
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default: |
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if (writeflag == MEM_READ) { |
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debug("[ au1x00_uart%i: read from 0x%08lx ]\n", |
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d->uart_nr, (long)relative_addr); |
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} else { |
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debug("[ au1x00_uart%i: write to 0x%08lx: 0x%08llx" |
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" ]\n", d->uart_nr, (long)relative_addr, |
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(long long)idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_au1x00_pc_tick(): |
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* |
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* Cause periodic ticks. (The PC is supposed to give interrupts at |
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* 32768 Hz?) |
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*/ |
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void dev_au1x00_pc_tick(struct cpu *cpu, void *extra) |
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{ |
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struct au1x00_pc_data *d = extra; |
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|
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if (d->reg[PC_COUNTER_CONTROL/4] & CC_EN1) |
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cpu_interrupt(cpu, 8 + d->irq_nr); |
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} |
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|
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|
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/* |
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* dev_au1x00_pc_access(): |
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* |
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* Programmable Counters. |
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*/ |
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int dev_au1x00_pc_access(struct cpu *cpu, struct memory *mem, |
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uint64_t relative_addr, unsigned char *data, size_t len, |
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int writeflag, void *extra) |
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{ |
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struct au1x00_pc_data *d = extra; |
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uint64_t idata = 0, odata = 0; |
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|
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idata = memory_readmax64(cpu, data, len); |
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|
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if (writeflag == MEM_READ) |
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odata = d->reg[relative_addr / sizeof(uint32_t)]; |
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else |
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d->reg[relative_addr / sizeof(uint32_t)] = idata; |
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|
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switch (relative_addr) { |
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default: |
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if (writeflag == MEM_READ) { |
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debug("[ au1x00_pc: read from 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, odata); |
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} else { |
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debug("[ au1x00_pc: write to 0x%08lx: 0x%08x ]\n", |
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(long)relative_addr, idata); |
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} |
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} |
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|
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if (writeflag == MEM_READ) |
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memory_writemax64(cpu, data, len, odata); |
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|
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return 1; |
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} |
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|
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|
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/* |
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* dev_au1x00_init(): |
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*/ |
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struct au1x00_ic_data *dev_au1x00_init(struct machine *machine, |
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struct memory *mem) |
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{ |
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struct au1x00_ic_data *d_ic0; |
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struct au1x00_ic_data *d_ic1; |
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struct au1x00_uart_data *d0; |
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struct au1x00_uart_data *d1; |
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struct au1x00_uart_data *d2; |
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struct au1x00_uart_data *d3; |
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struct au1x00_pc_data *d_pc; |
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|
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d_ic0 = malloc(sizeof(struct au1x00_ic_data)); |
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d_ic1 = malloc(sizeof(struct au1x00_ic_data)); |
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d0 = malloc(sizeof(struct au1x00_uart_data)); |
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d1 = malloc(sizeof(struct au1x00_uart_data)); |
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d2 = malloc(sizeof(struct au1x00_uart_data)); |
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d3 = malloc(sizeof(struct au1x00_uart_data)); |
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d_pc = malloc(sizeof(struct au1x00_pc_data)); |
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|
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if (d0 == NULL || d1 == NULL || d2 == NULL || |
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d3 == NULL || d_pc == NULL || d_ic0 == NULL |
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|| d_ic1 == NULL) { |
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fprintf(stderr, "out of memory\n"); |
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exit(1); |
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} |
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memset(d_ic0, 0, sizeof(struct au1x00_ic_data)); |
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memset(d_ic1, 0, sizeof(struct au1x00_ic_data)); |
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memset(d0, 0, sizeof(struct au1x00_uart_data)); |
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memset(d1, 0, sizeof(struct au1x00_uart_data)); |
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memset(d2, 0, sizeof(struct au1x00_uart_data)); |
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memset(d3, 0, sizeof(struct au1x00_uart_data)); |
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memset(d_pc, 0, sizeof(struct au1x00_pc_data)); |
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|
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d_ic0->ic_nr = 0; |
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d_ic1->ic_nr = 1; |
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|
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d0->uart_nr = 0; d0->irq_nr = 0; |
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d1->uart_nr = 1; d1->irq_nr = 1; |
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d2->uart_nr = 2; d2->irq_nr = 2; |
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d3->uart_nr = 3; d3->irq_nr = 3; |
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|
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d0->console_handle = console_start_slave(machine, "AU1x00 port 0"); |
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d1->console_handle = console_start_slave(machine, "AU1x00 port 1"); |
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d2->console_handle = console_start_slave(machine, "AU1x00 port 2"); |
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d3->console_handle = console_start_slave(machine, "AU1x00 port 3"); |
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|
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d_pc->irq_nr = 14; |
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|
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memory_device_register(mem, "au1x00_ic0", |
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IC0_BASE, 0x100, dev_au1x00_ic_access, d_ic0, MEM_DEFAULT, NULL); |
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memory_device_register(mem, "au1x00_ic1", |
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IC1_BASE, 0x100, dev_au1x00_ic_access, d_ic1, MEM_DEFAULT, NULL); |
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|
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memory_device_register(mem, "au1x00_uart0", UART0_BASE, UART_SIZE, |
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dev_au1x00_uart_access, d0, MEM_DEFAULT, NULL); |
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memory_device_register(mem, "au1x00_uart1", UART1_BASE, UART_SIZE, |
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dev_au1x00_uart_access, d1, MEM_DEFAULT, NULL); |
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memory_device_register(mem, "au1x00_uart2", UART2_BASE, UART_SIZE, |
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dev_au1x00_uart_access, d2, MEM_DEFAULT, NULL); |
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memory_device_register(mem, "au1x00_uart3", UART3_BASE, UART_SIZE, |
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dev_au1x00_uart_access, d3, MEM_DEFAULT, NULL); |
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|
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memory_device_register(mem, "au1x00_pc", PC_BASE, PC_SIZE + 0x8, |
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dev_au1x00_pc_access, d_pc, MEM_DEFAULT, NULL); |
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machine_add_tickfunction(machine, dev_au1x00_pc_tick, d_pc, 15); |
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|
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return d_ic0; |
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} |
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