1 |
/* |
/* |
2 |
* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
3 |
* |
* |
4 |
* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
5 |
* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
25 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
26 |
* |
* |
27 |
* |
* |
28 |
* $Id: memory_rw.c,v 1.65 2005/10/10 18:43:36 debug Exp $ |
* $Id: memory_rw.c,v 1.95 2006/07/25 21:49:14 debug Exp $ |
29 |
* |
* |
30 |
* Generic memory_rw(), with special hacks for specific CPU families. |
* Generic memory_rw(), with special hacks for specific CPU families. |
31 |
* |
* |
48 |
* a placeholder for data when reading from memory |
* a placeholder for data when reading from memory |
49 |
* len the length of the 'data' buffer |
* len the length of the 'data' buffer |
50 |
* writeflag set to MEM_READ or MEM_WRITE |
* writeflag set to MEM_READ or MEM_WRITE |
51 |
* cache_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
* misc_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
52 |
* |
* |
53 |
* If the address indicates access to a memory mapped device, that device' |
* If the address indicates access to a memory mapped device, that device' |
54 |
* read/write access function is called. |
* read/write access function is called. |
55 |
* |
* |
|
* If instruction latency/delay support is enabled, then |
|
|
* cpu->instruction_delay is increased by the number of instruction to |
|
|
* delay execution. |
|
|
* |
|
56 |
* This function should not be called with cpu == NULL. |
* This function should not be called with cpu == NULL. |
57 |
* |
* |
58 |
* Returns one of the following: |
* Returns one of the following: |
62 |
* (MEMORY_ACCESS_FAILED is 0.) |
* (MEMORY_ACCESS_FAILED is 0.) |
63 |
*/ |
*/ |
64 |
int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
65 |
unsigned char *data, size_t len, int writeflag, int cache_flags) |
unsigned char *data, size_t len, int writeflag, int misc_flags) |
66 |
{ |
{ |
67 |
#ifdef MEM_ALPHA |
#ifdef MEM_ALPHA |
68 |
const int offset_mask = 0x1fff; |
const int offset_mask = 0x1fff; |
76 |
uint64_t paddr; |
uint64_t paddr; |
77 |
int cache, no_exceptions, offset; |
int cache, no_exceptions, offset; |
78 |
unsigned char *memblock; |
unsigned char *memblock; |
79 |
#ifdef MEM_MIPS |
int dyntrans_device_danger = 0; |
|
int bintrans_cached = cpu->machine->bintrans_enable; |
|
|
#endif |
|
|
int bintrans_device_danger = 0; |
|
80 |
|
|
81 |
no_exceptions = cache_flags & NO_EXCEPTIONS; |
no_exceptions = misc_flags & NO_EXCEPTIONS; |
82 |
cache = cache_flags & CACHE_FLAGS_MASK; |
cache = misc_flags & CACHE_FLAGS_MASK; |
83 |
|
|
84 |
#ifdef MEM_X86 |
#ifdef MEM_X86 |
85 |
/* Real-mode wrap-around: */ |
/* Real-mode wrap-around: */ |
86 |
if (REAL_MODE && !(cache_flags & PHYSICAL)) { |
if (REAL_MODE && !(misc_flags & PHYSICAL)) { |
87 |
if ((vaddr & 0xffff) + len > 0x10000) { |
if ((vaddr & 0xffff) + len > 0x10000) { |
88 |
/* Do one byte at a time: */ |
/* Do one byte at a time: */ |
89 |
int res = 0, i; |
int res = 0; |
90 |
|
size_t i; |
91 |
for (i=0; i<len; i++) |
for (i=0; i<len; i++) |
92 |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
93 |
writeflag, cache_flags); |
writeflag, misc_flags); |
94 |
return res; |
return res; |
95 |
} |
} |
96 |
} |
} |
97 |
|
|
98 |
/* Crossing a page boundary? Then do one byte at a time: */ |
/* Crossing a page boundary? Then do one byte at a time: */ |
99 |
if ((vaddr & 0xfff) + len > 0x1000 && !(cache_flags & PHYSICAL) |
if ((vaddr & 0xfff) + len > 0x1000 && !(misc_flags & PHYSICAL) |
100 |
&& cpu->cd.x86.cr[0] & X86_CR0_PG) { |
&& cpu->cd.x86.cr[0] & X86_CR0_PG) { |
101 |
/* For WRITES: Read ALL BYTES FIRST and write them back!!! |
/* For WRITES: Read ALL BYTES FIRST and write them back!!! |
102 |
Then do a write of all the new bytes. This is to make sure |
Then do a write of all the new bytes. This is to make sure |
103 |
than both pages around the boundary are writable so we don't |
than both pages around the boundary are writable so we don't |
104 |
do a partial write. */ |
do a partial write. */ |
105 |
int res = 0, i; |
int res = 0; |
106 |
|
size_t i; |
107 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
108 |
unsigned char tmp; |
unsigned char tmp; |
109 |
for (i=0; i<len; i++) { |
for (i=0; i<len; i++) { |
110 |
res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
111 |
MEM_READ, cache_flags); |
MEM_READ, misc_flags); |
112 |
if (!res) |
if (!res) |
113 |
return 0; |
return 0; |
114 |
res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
115 |
MEM_WRITE, cache_flags); |
MEM_WRITE, misc_flags); |
116 |
if (!res) |
if (!res) |
117 |
return 0; |
return 0; |
118 |
} |
} |
119 |
for (i=0; i<len; i++) { |
for (i=0; i<len; i++) { |
120 |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
121 |
MEM_WRITE, cache_flags); |
MEM_WRITE, misc_flags); |
122 |
if (!res) |
if (!res) |
123 |
return 0; |
return 0; |
124 |
} |
} |
126 |
for (i=0; i<len; i++) { |
for (i=0; i<len; i++) { |
127 |
/* Do one byte at a time: */ |
/* Do one byte at a time: */ |
128 |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
129 |
writeflag, cache_flags); |
writeflag, misc_flags); |
130 |
if (!res) { |
if (!res) { |
131 |
if (cache == CACHE_INSTRUCTION) { |
if (cache == CACHE_INSTRUCTION) { |
132 |
fatal("FAILED instruction " |
fatal("FAILED instruction " |
143 |
} |
} |
144 |
#endif /* X86 */ |
#endif /* X86 */ |
145 |
|
|
|
#ifdef MEM_MIPS |
|
|
if (bintrans_cached) { |
|
|
if (cache == CACHE_INSTRUCTION) { |
|
|
cpu->cd.mips.pc_bintrans_host_4kpage = NULL; |
|
|
cpu->cd.mips.pc_bintrans_paddr_valid = 0; |
|
|
} |
|
|
} |
|
|
#endif /* MEM_MIPS */ |
|
146 |
|
|
147 |
#ifdef MEM_USERLAND |
#ifdef MEM_USERLAND |
148 |
#ifdef MEM_ALPHA |
#ifdef MEM_ALPHA |
150 |
#else |
#else |
151 |
paddr = vaddr & 0x7fffffff; |
paddr = vaddr & 0x7fffffff; |
152 |
#endif |
#endif |
153 |
goto have_paddr; |
#else /* !MEM_USERLAND */ |
154 |
#endif |
if (misc_flags & PHYSICAL || cpu->translate_v2p == NULL) { |
|
|
|
|
#ifndef MEM_USERLAND |
|
|
#ifdef MEM_MIPS |
|
|
/* |
|
|
* For instruction fetch, are we on the same page as the last |
|
|
* instruction we fetched? |
|
|
* |
|
|
* NOTE: There's no need to check this stuff here if this address |
|
|
* is known to be in host ram, as it's done at instruction fetch |
|
|
* time in cpu.c! Only check if _host_4k_page == NULL. |
|
|
*/ |
|
|
if (cache == CACHE_INSTRUCTION && |
|
|
cpu->cd.mips.pc_last_host_4k_page == NULL && |
|
|
(vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) { |
|
|
paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff); |
|
|
goto have_paddr; |
|
|
} |
|
|
#endif /* MEM_MIPS */ |
|
|
|
|
|
if (cache_flags & PHYSICAL || cpu->translate_address == NULL) { |
|
155 |
paddr = vaddr; |
paddr = vaddr; |
|
|
|
|
#ifdef MEM_ALPHA |
|
|
/* paddr &= 0x1fffffff; For testalpha */ |
|
|
paddr &= 0x000003ffffffffffULL; |
|
|
#endif |
|
|
|
|
|
#ifdef MEM_IA64 |
|
|
/* For testia64 */ |
|
|
paddr &= 0x3fffffff; |
|
|
#endif |
|
|
|
|
|
#ifdef MEM_PPC |
|
|
if (cpu->cd.ppc.bits == 32) |
|
|
paddr &= 0xffffffff; |
|
|
#endif |
|
|
|
|
|
#ifdef MEM_SH |
|
|
paddr &= 0xffffffff; |
|
|
#endif |
|
156 |
} else { |
} else { |
157 |
ok = cpu->translate_address(cpu, vaddr, &paddr, |
ok = cpu->translate_v2p(cpu, vaddr, &paddr, |
158 |
(writeflag? FLAG_WRITEFLAG : 0) + |
(writeflag? FLAG_WRITEFLAG : 0) + |
159 |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
160 |
#ifdef MEM_X86 |
#ifdef MEM_X86 |
161 |
+ (cache_flags & NO_SEGMENTATION) |
+ (misc_flags & NO_SEGMENTATION) |
162 |
#endif |
#endif |
163 |
#ifdef MEM_ARM |
#ifdef MEM_ARM |
164 |
+ (cache_flags & MEMORY_USER_ACCESS) |
+ (misc_flags & MEMORY_USER_ACCESS) |
165 |
#endif |
#endif |
166 |
+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
167 |
/* If the translation caused an exception, or was invalid in |
/* If the translation caused an exception, or was invalid in |
174 |
|
|
175 |
#ifdef MEM_X86 |
#ifdef MEM_X86 |
176 |
/* DOS debugging :-) */ |
/* DOS debugging :-) */ |
177 |
if (!quiet_mode && !(cache_flags & PHYSICAL)) { |
if (!quiet_mode && !(misc_flags & PHYSICAL)) { |
178 |
if (paddr >= 0x400 && paddr <= 0x4ff) |
if (paddr >= 0x400 && paddr <= 0x4ff) |
179 |
debug("{ PC BIOS DATA AREA: %s 0x%x }\n", writeflag == |
debug("{ PC BIOS DATA AREA: %s 0x%x }\n", writeflag == |
180 |
MEM_WRITE? "writing to" : "reading from", |
MEM_WRITE? "writing to" : "reading from", |
187 |
#endif |
#endif |
188 |
} |
} |
189 |
#endif |
#endif |
190 |
|
#endif /* !MEM_USERLAND */ |
|
#ifdef MEM_MIPS |
|
|
/* |
|
|
* If correct cache emulation is enabled, and we need to simluate |
|
|
* cache misses even from the instruction cache, we can't run directly |
|
|
* from a host page. :-/ |
|
|
*/ |
|
|
#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS) |
|
|
#else |
|
|
if (cache == CACHE_INSTRUCTION) { |
|
|
cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff; |
|
|
cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff; |
|
|
cpu->cd.mips.pc_last_host_4k_page = NULL; |
|
|
|
|
|
/* _last_host_4k_page will be set to 1 further down, |
|
|
if the page is actually in host ram */ |
|
|
} |
|
|
#endif |
|
|
#endif /* MEM_MIPS */ |
|
|
#endif /* ifndef MEM_USERLAND */ |
|
|
|
|
|
|
|
|
#if defined(MEM_MIPS) || defined(MEM_USERLAND) |
|
|
have_paddr: |
|
|
#endif |
|
|
|
|
|
|
|
|
#ifdef MEM_MIPS |
|
|
/* TODO: How about bintrans vs cache emulation? */ |
|
|
if (bintrans_cached) { |
|
|
if (cache == CACHE_INSTRUCTION) { |
|
|
cpu->cd.mips.pc_bintrans_paddr_valid = 1; |
|
|
cpu->cd.mips.pc_bintrans_paddr = paddr; |
|
|
} |
|
|
} |
|
|
#endif /* MEM_MIPS */ |
|
|
|
|
191 |
|
|
192 |
|
|
193 |
#ifndef MEM_USERLAND |
#ifndef MEM_USERLAND |
194 |
/* |
/* |
195 |
* Memory mapped device? |
* Memory mapped device? |
196 |
* |
* |
197 |
* TODO: this is utterly slow. |
* TODO: if paddr < base, but len enough, then the device should |
198 |
* TODO2: if paddr<base, but len enough, then we should write |
* still be written to! |
|
* to a device to |
|
199 |
*/ |
*/ |
200 |
if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
201 |
uint64_t orig_paddr = paddr; |
uint64_t orig_paddr = paddr; |
202 |
int i, start, res; |
int i, start, end, res; |
203 |
|
|
204 |
/* |
/* |
205 |
* Really really slow, but unfortunately necessary. This is |
* Really really slow, but unfortunately necessary. This is |
209 |
* b) offsets 0x124..0x777 are a device |
* b) offsets 0x124..0x777 are a device |
210 |
* |
* |
211 |
* 1) a read is done from offset 0x100. the page is |
* 1) a read is done from offset 0x100. the page is |
212 |
* added to the bintrans system as a "RAM" page |
* added to the dyntrans system as a "RAM" page |
213 |
* 2) a bintranslated read is done from offset 0x200, |
* 2) a dyntranslated read is done from offset 0x200, |
214 |
* which should access the device, but since the |
* which should access the device, but since the |
215 |
* entire page is added, it will access non-existant |
* entire page is added, it will access non-existant |
216 |
* RAM instead, without warning. |
* RAM instead, without warning. |
217 |
* |
* |
218 |
* Setting bintrans_device_danger = 1 on accesses which are |
* Setting dyntrans_device_danger = 1 on accesses which are |
219 |
* on _any_ offset on pages that are device mapped avoids |
* on _any_ offset on pages that are device mapped avoids |
220 |
* this problem, but it is probably not very fast. |
* this problem, but it is probably not very fast. |
221 |
|
* |
222 |
|
* TODO: Convert this into a quick (multi-level, 64-bit) |
223 |
|
* address space lookup, to find dangerous pages. |
224 |
*/ |
*/ |
225 |
|
#if 1 |
226 |
for (i=0; i<mem->n_mmapped_devices; i++) |
for (i=0; i<mem->n_mmapped_devices; i++) |
227 |
if (paddr >= (mem->dev_baseaddr[i] & ~offset_mask) && |
if (paddr >= (mem->dev_baseaddr[i] & ~offset_mask) && |
228 |
paddr <= ((mem->dev_baseaddr[i] + |
paddr <= ((mem->dev_endaddr[i]-1) | offset_mask)) { |
229 |
mem->dev_length[i] - 1) | offset_mask)) { |
dyntrans_device_danger = 1; |
|
bintrans_device_danger = 1; |
|
230 |
break; |
break; |
231 |
} |
} |
232 |
|
#endif |
233 |
|
|
234 |
i = start = mem->last_accessed_device; |
start = 0; end = mem->n_mmapped_devices - 1; |
235 |
|
i = mem->last_accessed_device; |
236 |
|
|
237 |
/* Scan through all devices: */ |
/* Scan through all devices: */ |
238 |
do { |
do { |
239 |
if (paddr >= mem->dev_baseaddr[i] && |
if (paddr >= mem->dev_baseaddr[i] && |
240 |
paddr < mem->dev_baseaddr[i] + mem->dev_length[i]) { |
paddr < mem->dev_endaddr[i]) { |
241 |
/* Found a device, let's access it: */ |
/* Found a device, let's access it: */ |
242 |
mem->last_accessed_device = i; |
mem->last_accessed_device = i; |
243 |
|
|
246 |
len = mem->dev_length[i] - paddr; |
len = mem->dev_length[i] - paddr; |
247 |
|
|
248 |
if (cpu->update_translation_table != NULL && |
if (cpu->update_translation_table != NULL && |
249 |
mem->dev_flags[i] & MEM_DYNTRANS_OK) { |
!(ok & MEMORY_NOT_FULL_PAGE) && |
250 |
|
mem->dev_flags[i] & DM_DYNTRANS_OK) { |
251 |
int wf = writeflag == MEM_WRITE? 1 : 0; |
int wf = writeflag == MEM_WRITE? 1 : 0; |
252 |
|
unsigned char *host_addr; |
253 |
|
|
254 |
if (writeflag) { |
if (!(mem->dev_flags[i] & |
255 |
|
DM_DYNTRANS_WRITE_OK)) |
256 |
|
wf = 0; |
257 |
|
|
258 |
|
if (writeflag && wf) { |
259 |
if (paddr < mem-> |
if (paddr < mem-> |
260 |
dev_dyntrans_write_low[i]) |
dev_dyntrans_write_low[i]) |
261 |
mem-> |
mem-> |
270 |
offset_mask; |
offset_mask; |
271 |
} |
} |
272 |
|
|
273 |
if (!(mem->dev_flags[i] & |
if (mem->dev_flags[i] & |
274 |
MEM_DYNTRANS_WRITE_OK)) |
DM_EMULATED_RAM) { |
275 |
wf = 0; |
/* MEM_WRITE to force the page |
276 |
|
to be allocated, if it |
277 |
|
wasn't already */ |
278 |
|
uint64_t *pp = (uint64_t *) |
279 |
|
mem->dev_dyntrans_data[i]; |
280 |
|
uint64_t p = orig_paddr - *pp; |
281 |
|
host_addr = |
282 |
|
memory_paddr_to_hostaddr( |
283 |
|
mem, p & ~offset_mask, |
284 |
|
MEM_WRITE); |
285 |
|
} else { |
286 |
|
host_addr = |
287 |
|
mem->dev_dyntrans_data[i] + |
288 |
|
(paddr & ~offset_mask); |
289 |
|
} |
290 |
|
|
291 |
cpu->update_translation_table(cpu, |
cpu->update_translation_table(cpu, |
292 |
vaddr & ~offset_mask, |
vaddr & ~offset_mask, host_addr, |
|
mem->dev_dyntrans_data[i] + |
|
|
(paddr & ~offset_mask), |
|
293 |
wf, orig_paddr & ~offset_mask); |
wf, orig_paddr & ~offset_mask); |
294 |
} |
} |
295 |
|
|
296 |
res = 0; |
res = 0; |
297 |
if (!no_exceptions || (mem->dev_flags[i] & |
if (!no_exceptions || (mem->dev_flags[i] & |
298 |
MEM_READING_HAS_NO_SIDE_EFFECTS)) |
DM_READS_HAVE_NO_SIDE_EFFECTS)) |
299 |
res = mem->dev_f[i](cpu, mem, paddr, |
res = mem->dev_f[i](cpu, mem, paddr, |
300 |
data, len, writeflag, |
data, len, writeflag, |
301 |
mem->dev_extra[i]); |
mem->dev_extra[i]); |
302 |
|
|
|
#ifdef ENABLE_INSTRUCTION_DELAYS |
|
303 |
if (res == 0) |
if (res == 0) |
304 |
res = -1; |
res = -1; |
305 |
|
|
|
cpu->cd.mips.instruction_delay += |
|
|
( (abs(res) - 1) * |
|
|
cpu->cd.mips.cpu_type.instrs_per_cycle ); |
|
|
#endif |
|
|
|
|
306 |
#ifndef MEM_X86 |
#ifndef MEM_X86 |
307 |
/* |
/* |
308 |
* If accessing the memory mapped device |
* If accessing the memory mapped device |
323 |
goto do_return_ok; |
goto do_return_ok; |
324 |
} |
} |
325 |
|
|
326 |
i ++; |
if (paddr < mem->dev_baseaddr[i]) |
327 |
if (i == mem->n_mmapped_devices) |
end = i - 1; |
328 |
i = 0; |
if (paddr >= mem->dev_endaddr[i]) |
329 |
} while (i != start); |
start = i + 1; |
330 |
|
i = (start + end) >> 1; |
331 |
|
} while (start <= end); |
332 |
} |
} |
333 |
|
|
334 |
|
|
340 |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
switch (cpu->cd.mips.cpu_type.mmu_model) { |
341 |
case MMU3K: |
case MMU3K: |
342 |
/* if not uncached addess (TODO: generalize this) */ |
/* if not uncached addess (TODO: generalize this) */ |
343 |
if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE && |
if (!(misc_flags & PHYSICAL) && cache != CACHE_NONE && |
344 |
!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
345 |
(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
346 |
if (memory_cache_R3000(cpu, cache, paddr, |
if (memory_cache_R3000(cpu, cache, paddr, |
371 |
#endif /* MIPS */ |
#endif /* MIPS */ |
372 |
{ |
{ |
373 |
if (paddr >= mem->physical_max) { |
if (paddr >= mem->physical_max) { |
374 |
|
uint64_t offset, old_pc = cpu->pc; |
375 |
char *symbol; |
char *symbol; |
|
uint64_t old_pc; |
|
|
uint64_t offset; |
|
|
|
|
|
#ifdef MEM_MIPS |
|
|
old_pc = cpu->cd.mips.pc_last; |
|
|
#else |
|
|
/* Default instruction size on most |
|
|
RISC archs is 32 bits: */ |
|
|
old_pc = cpu->pc - sizeof(uint32_t); |
|
|
#endif |
|
376 |
|
|
377 |
/* This allows for example OS kernels to probe |
/* This allows for example OS kernels to probe |
378 |
memory a few KBs past the end of memory, |
memory a few KBs past the end of memory, |
419 |
fatal(" <%s> ]\n", |
fatal(" <%s> ]\n", |
420 |
symbol? symbol : " no symbol "); |
symbol? symbol : " no symbol "); |
421 |
} |
} |
|
|
|
|
if (cpu->machine->single_step_on_bad_addr) { |
|
|
fatal("[ unimplemented access to " |
|
|
"0x%llx, pc=0x",(long long)paddr); |
|
|
if (cpu->is_32bit) |
|
|
fatal("%08x ]\n", |
|
|
(int)old_pc); |
|
|
else |
|
|
fatal("%016llx ]\n", |
|
|
(long long)old_pc); |
|
|
single_step = 1; |
|
|
} |
|
422 |
} |
} |
423 |
|
|
424 |
if (writeflag == MEM_READ) { |
if (writeflag == MEM_READ) { |
459 |
|
|
460 |
/* |
/* |
461 |
* Uncached access: |
* Uncached access: |
462 |
|
* |
463 |
|
* 1) Translate the physical address to a host address. |
464 |
|
* |
465 |
|
* 2) Insert this virtual->physical->host translation into the |
466 |
|
* fast translation arrays (using update_translation_table()). |
467 |
|
* |
468 |
|
* 3) If this was a Write, then invalidate any code translations |
469 |
|
* in that page. |
470 |
*/ |
*/ |
471 |
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
memblock = memory_paddr_to_hostaddr(mem, paddr & ~offset_mask, |
472 |
|
writeflag); |
473 |
if (memblock == NULL) { |
if (memblock == NULL) { |
474 |
if (writeflag == MEM_READ) |
if (writeflag == MEM_READ) |
475 |
memset(data, 0, len); |
memset(data, 0, len); |
476 |
goto do_return_ok; |
goto do_return_ok; |
477 |
} |
} |
478 |
|
|
479 |
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
offset = paddr & offset_mask; |
480 |
|
|
481 |
if (cpu->update_translation_table != NULL && !bintrans_device_danger |
if (cpu->update_translation_table != NULL && !dyntrans_device_danger |
482 |
|
#ifdef MEM_MIPS |
483 |
|
/* Ugly hack for R2000/R3000 caches: */ |
484 |
|
&& (cpu->cd.mips.cpu_type.mmu_model != MMU3K || |
485 |
|
!(cpu->cd.mips.coproc[0]->reg[COP0_STATUS] & MIPS1_ISOL_CACHES)) |
486 |
|
#endif |
487 |
|
#ifndef MEM_MIPS |
488 |
|
/* && !(misc_flags & MEMORY_USER_ACCESS) */ |
489 |
|
#ifndef MEM_USERLAND |
490 |
|
&& !(ok & MEMORY_NOT_FULL_PAGE) |
491 |
|
#endif |
492 |
|
#endif |
493 |
&& !no_exceptions) |
&& !no_exceptions) |
494 |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
495 |
memblock + (offset & ~offset_mask), |
memblock, (misc_flags & MEMORY_USER_ACCESS) | |
496 |
#if 0 |
#if !defined(MEM_MIPS) && !defined(MEM_USERLAND) |
497 |
cache == CACHE_INSTRUCTION? |
(cache == CACHE_INSTRUCTION? |
498 |
(writeflag == MEM_WRITE? 1 : 0) |
(writeflag == MEM_WRITE? 1 : 0) : ok - 1), |
|
: ok - 1, |
|
499 |
#else |
#else |
500 |
writeflag == MEM_WRITE? 1 : 0, |
(writeflag == MEM_WRITE? 1 : 0), |
501 |
#endif |
#endif |
502 |
paddr & ~offset_mask); |
paddr & ~offset_mask); |
503 |
|
|
504 |
if (writeflag == MEM_WRITE && |
/* Invalidate code translations for the page we are writing to. */ |
505 |
cpu->invalidate_code_translation != NULL) |
if (writeflag == MEM_WRITE && cpu->invalidate_code_translation != NULL) |
506 |
cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); |
cpu->invalidate_code_translation(cpu, paddr, INVALIDATE_PADDR); |
507 |
|
|
508 |
|
if ((paddr&((1<<BITS_PER_MEMBLOCK)-1)) + len > (1<<BITS_PER_MEMBLOCK)) { |
509 |
|
printf("Write over memblock boundary?\n"); |
510 |
|
exit(1); |
511 |
|
} |
512 |
|
|
513 |
if (writeflag == MEM_WRITE) { |
if (writeflag == MEM_WRITE) { |
514 |
/* Ugly optimization, but it works: */ |
/* Ugly optimization, but it works: */ |
515 |
if (len == sizeof(uint32_t) && (offset & 3)==0 |
if (len == sizeof(uint32_t) && (offset & 3)==0 |
528 |
*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
529 |
else |
else |
530 |
memcpy(data, memblock + offset, len); |
memcpy(data, memblock + offset, len); |
|
|
|
|
#ifdef MEM_MIPS |
|
|
if (cache == CACHE_INSTRUCTION) { |
|
|
cpu->cd.mips.pc_last_host_4k_page = memblock |
|
|
+ (offset & ~offset_mask); |
|
|
if (bintrans_cached) { |
|
|
cpu->cd.mips.pc_bintrans_host_4kpage = |
|
|
cpu->cd.mips.pc_last_host_4k_page; |
|
|
} |
|
|
} |
|
|
#endif /* MIPS */ |
|
531 |
} |
} |
532 |
|
|
533 |
|
|