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dpavlin |
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/* |
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* Copyright (C) 2003-2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: memory_rw.c,v 1.57 2005/08/12 21:57:02 debug Exp $ |
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dpavlin |
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* |
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* Generic memory_rw(), with special hacks for specific CPU families. |
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* |
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* Example for inclusion from memory_mips.c: |
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* |
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* MEMORY_RW should be mips_memory_rw |
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* MEM_MIPS should be defined |
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*/ |
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/* |
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* memory_rw(): |
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* |
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* Read or write data from/to memory. |
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* |
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* cpu the cpu doing the read/write |
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* mem the memory object to use |
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* vaddr the virtual address |
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* data a pointer to the data to be written to memory, or |
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* a placeholder for data when reading from memory |
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* len the length of the 'data' buffer |
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* writeflag set to MEM_READ or MEM_WRITE |
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* cache_flags CACHE_{NONE,DATA,INSTRUCTION} | other flags |
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* |
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* If the address indicates access to a memory mapped device, that device' |
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* read/write access function is called. |
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* |
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* If instruction latency/delay support is enabled, then |
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* cpu->instruction_delay is increased by the number of instruction to |
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* delay execution. |
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* |
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* This function should not be called with cpu == NULL. |
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* |
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* Returns one of the following: |
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* MEMORY_ACCESS_FAILED |
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* MEMORY_ACCESS_OK |
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* |
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* (MEMORY_ACCESS_FAILED is 0.) |
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*/ |
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int MEMORY_RW(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags) |
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{ |
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dpavlin |
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#ifdef MEM_ALPHA |
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const int offset_mask = 0x1fff; |
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#else |
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const int offset_mask = 0xfff; |
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#endif |
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dpavlin |
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#ifndef MEM_USERLAND |
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int ok = 1; |
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#endif |
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uint64_t paddr; |
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int cache, no_exceptions, offset; |
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unsigned char *memblock; |
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dpavlin |
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#ifdef MEM_MIPS |
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dpavlin |
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int bintrans_cached = cpu->machine->bintrans_enable; |
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dpavlin |
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#endif |
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dpavlin |
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int bintrans_device_danger = 0; |
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dpavlin |
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|
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dpavlin |
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no_exceptions = cache_flags & NO_EXCEPTIONS; |
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cache = cache_flags & CACHE_FLAGS_MASK; |
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dpavlin |
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#ifdef MEM_X86 |
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dpavlin |
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/* Real-mode wrap-around: */ |
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if (REAL_MODE && !(cache_flags & PHYSICAL)) { |
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if ((vaddr & 0xffff) + len > 0x10000) { |
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/* Do one byte at a time: */ |
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int res = 0, i; |
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for (i=0; i<len; i++) |
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res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
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writeflag, cache_flags); |
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return res; |
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} |
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} |
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dpavlin |
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dpavlin |
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/* Crossing a page boundary? Then do one byte at a time: */ |
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if ((vaddr & 0xfff) + len > 0x1000 && !(cache_flags & PHYSICAL) |
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&& cpu->cd.x86.cr[0] & X86_CR0_PG) { |
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/* For WRITES: Read ALL BYTES FIRST and write them back!!! |
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Then do a write of all the new bytes. This is to make sure |
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than both pages around the boundary are writable so we don't |
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do a partial write. */ |
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int res = 0, i; |
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if (writeflag == MEM_WRITE) { |
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unsigned char tmp; |
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for (i=0; i<len; i++) { |
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res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
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MEM_READ, cache_flags); |
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if (!res) |
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dpavlin |
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return 0; |
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dpavlin |
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res = MEMORY_RW(cpu, mem, vaddr+i, &tmp, 1, |
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MEM_WRITE, cache_flags); |
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if (!res) |
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return 0; |
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} |
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for (i=0; i<len; i++) { |
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res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
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MEM_WRITE, cache_flags); |
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if (!res) |
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return 0; |
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} |
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} else { |
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for (i=0; i<len; i++) { |
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/* Do one byte at a time: */ |
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res = MEMORY_RW(cpu, mem, vaddr+i, &data[i], 1, |
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writeflag, cache_flags); |
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if (!res) { |
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if (cache == CACHE_INSTRUCTION) { |
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fatal("FAILED instruction " |
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"fetch across page boundar" |
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"y: todo. vaddr=0x%08x\n", |
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(int)vaddr); |
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cpu->running = 0; |
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} |
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return 0; |
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dpavlin |
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} |
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} |
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} |
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dpavlin |
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return res; |
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dpavlin |
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} |
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dpavlin |
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#endif /* X86 */ |
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dpavlin |
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|
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dpavlin |
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#ifdef MEM_MIPS |
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if (bintrans_cached) { |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_host_4kpage = NULL; |
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cpu->cd.mips.pc_bintrans_paddr_valid = 0; |
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} |
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} |
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#endif /* MEM_MIPS */ |
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#ifdef MEM_USERLAND |
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dpavlin |
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#ifdef MEM_ALPHA |
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paddr = vaddr; |
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#else |
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dpavlin |
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paddr = vaddr & 0x7fffffff; |
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dpavlin |
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#endif |
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dpavlin |
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goto have_paddr; |
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#endif |
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#ifndef MEM_USERLAND |
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#ifdef MEM_MIPS |
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/* |
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* For instruction fetch, are we on the same page as the last |
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* instruction we fetched? |
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* |
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* NOTE: There's no need to check this stuff here if this address |
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* is known to be in host ram, as it's done at instruction fetch |
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* time in cpu.c! Only check if _host_4k_page == NULL. |
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*/ |
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if (cache == CACHE_INSTRUCTION && |
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cpu->cd.mips.pc_last_host_4k_page == NULL && |
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(vaddr & ~0xfff) == cpu->cd.mips.pc_last_virtual_page) { |
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paddr = cpu->cd.mips.pc_last_physical_page | (vaddr & 0xfff); |
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goto have_paddr; |
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} |
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#endif /* MEM_MIPS */ |
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if (cache_flags & PHYSICAL || cpu->translate_address == NULL) { |
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paddr = vaddr; |
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dpavlin |
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#ifdef MEM_ALPHA |
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/* paddr &= 0x1fffffff; For testalpha */ |
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paddr &= 0x000003ffffffffffULL; |
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#endif |
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#ifdef MEM_ARM |
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paddr &= 0x3fffffff; |
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#endif |
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#ifdef MEM_IA64 |
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/* For testia64 */ |
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paddr &= 0x3fffffff; |
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#endif |
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#ifdef MEM_PPC |
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if (cpu->cd.ppc.bits == 32) |
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paddr &= 0xffffffff; |
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#endif |
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dpavlin |
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} else { |
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ok = cpu->translate_address(cpu, vaddr, &paddr, |
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(writeflag? FLAG_WRITEFLAG : 0) + |
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(no_exceptions? FLAG_NOEXCEPTIONS : 0) |
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dpavlin |
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#ifdef MEM_X86 |
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+ (cache_flags & NO_SEGMENTATION) |
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#endif |
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dpavlin |
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+ (cache==CACHE_INSTRUCTION? FLAG_INSTR : 0)); |
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/* If the translation caused an exception, or was invalid in |
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some way, we simply return without doing the memory |
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access: */ |
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if (!ok) |
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return MEMORY_ACCESS_FAILED; |
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} |
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dpavlin |
6 |
#ifdef MEM_X86 |
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/* DOS debugging :-) */ |
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if (!quiet_mode && !(cache_flags & PHYSICAL)) { |
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if (paddr >= 0x400 && paddr <= 0x4ff) |
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debug("{ PC BIOS DATA AREA: %s 0x%x }\n", writeflag == |
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MEM_WRITE? "writing to" : "reading from", |
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(int)paddr); |
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#if 0 |
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if (paddr >= 0xf0000 && paddr <= 0xfffff) |
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debug("{ BIOS ACCESS: %s 0x%x }\n", |
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writeflag == MEM_WRITE? "writing to" : |
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"reading from", (int)paddr); |
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#endif |
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} |
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#endif |
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dpavlin |
2 |
#ifdef MEM_MIPS |
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/* |
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* If correct cache emulation is enabled, and we need to simluate |
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* cache misses even from the instruction cache, we can't run directly |
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* from a host page. :-/ |
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*/ |
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#if defined(ENABLE_CACHE_EMULATION) && defined(ENABLE_INSTRUCTION_DELAYS) |
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#else |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_last_virtual_page = vaddr & ~0xfff; |
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cpu->cd.mips.pc_last_physical_page = paddr & ~0xfff; |
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cpu->cd.mips.pc_last_host_4k_page = NULL; |
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254 |
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/* _last_host_4k_page will be set to 1 further down, |
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if the page is actually in host ram */ |
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} |
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#endif |
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#endif /* MEM_MIPS */ |
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#endif /* ifndef MEM_USERLAND */ |
260 |
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dpavlin |
4 |
#if defined(MEM_MIPS) || defined(MEM_USERLAND) |
263 |
dpavlin |
2 |
have_paddr: |
264 |
dpavlin |
4 |
#endif |
265 |
dpavlin |
2 |
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266 |
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267 |
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#ifdef MEM_MIPS |
268 |
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/* TODO: How about bintrans vs cache emulation? */ |
269 |
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if (bintrans_cached) { |
270 |
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if (cache == CACHE_INSTRUCTION) { |
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cpu->cd.mips.pc_bintrans_paddr_valid = 1; |
272 |
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cpu->cd.mips.pc_bintrans_paddr = paddr; |
273 |
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} |
274 |
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} |
275 |
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#endif /* MEM_MIPS */ |
276 |
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277 |
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278 |
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279 |
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#ifndef MEM_USERLAND |
280 |
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/* |
281 |
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* Memory mapped device? |
282 |
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* |
283 |
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* TODO: this is utterly slow. |
284 |
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* TODO2: if paddr<base, but len enough, then we should write |
285 |
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* to a device to |
286 |
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*/ |
287 |
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if (paddr >= mem->mmap_dev_minaddr && paddr < mem->mmap_dev_maxaddr) { |
288 |
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uint64_t orig_paddr = paddr; |
289 |
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int i, start, res; |
290 |
dpavlin |
4 |
|
291 |
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/* |
292 |
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* Really really slow, but unfortunately necessary. This is |
293 |
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* to avoid the folowing scenario: |
294 |
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* |
295 |
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* a) offsets 0x000..0x123 are normal memory |
296 |
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* b) offsets 0x124..0x777 are a device |
297 |
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* |
298 |
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* 1) a read is done from offset 0x100. the page is |
299 |
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* added to the bintrans system as a "RAM" page |
300 |
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* 2) a bintranslated read is done from offset 0x200, |
301 |
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* which should access the device, but since the |
302 |
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* entire page is added, it will access non-existant |
303 |
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* RAM instead, without warning. |
304 |
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* |
305 |
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* Setting bintrans_device_danger = 1 on accesses which are |
306 |
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* on _any_ offset on pages that are device mapped avoids |
307 |
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* this problem, but it is probably not very fast. |
308 |
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*/ |
309 |
dpavlin |
12 |
for (i=0; i<mem->n_mmapped_devices; i++) |
310 |
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if (paddr >= (mem->dev_baseaddr[i] & ~offset_mask) && |
311 |
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paddr <= ((mem->dev_baseaddr[i] + |
312 |
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mem->dev_length[i] - 1) | offset_mask)) { |
313 |
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bintrans_device_danger = 1; |
314 |
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break; |
315 |
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} |
316 |
dpavlin |
4 |
|
317 |
dpavlin |
2 |
i = start = mem->last_accessed_device; |
318 |
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319 |
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/* Scan through all devices: */ |
320 |
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do { |
321 |
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if (paddr >= mem->dev_baseaddr[i] && |
322 |
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paddr < mem->dev_baseaddr[i] + mem->dev_length[i]) { |
323 |
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/* Found a device, let's access it: */ |
324 |
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mem->last_accessed_device = i; |
325 |
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326 |
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paddr -= mem->dev_baseaddr[i]; |
327 |
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if (paddr + len > mem->dev_length[i]) |
328 |
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len = mem->dev_length[i] - paddr; |
329 |
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|
330 |
dpavlin |
12 |
if (cpu->update_translation_table != NULL && |
331 |
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mem->dev_flags[i] & MEM_DYNTRANS_OK) { |
332 |
dpavlin |
2 |
int wf = writeflag == MEM_WRITE? 1 : 0; |
333 |
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|
334 |
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if (writeflag) { |
335 |
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if (paddr < mem-> |
336 |
dpavlin |
12 |
dev_dyntrans_write_low[i]) |
337 |
dpavlin |
2 |
mem-> |
338 |
dpavlin |
12 |
dev_dyntrans_write_low |
339 |
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[i] = paddr & |
340 |
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~offset_mask; |
341 |
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if (paddr >= mem-> |
342 |
|
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dev_dyntrans_write_high[i]) |
343 |
dpavlin |
2 |
mem-> |
344 |
dpavlin |
12 |
dev_dyntrans_write_high |
345 |
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[i] = paddr | |
346 |
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offset_mask; |
347 |
dpavlin |
2 |
} |
348 |
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|
349 |
|
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if (!(mem->dev_flags[i] & |
350 |
dpavlin |
12 |
MEM_DYNTRANS_WRITE_OK)) |
351 |
dpavlin |
2 |
wf = 0; |
352 |
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|
353 |
dpavlin |
12 |
cpu->update_translation_table(cpu, |
354 |
|
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vaddr & ~offset_mask, |
355 |
|
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mem->dev_dyntrans_data[i] + |
356 |
|
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(paddr & ~offset_mask), |
357 |
|
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wf, orig_paddr & ~offset_mask); |
358 |
dpavlin |
2 |
} |
359 |
|
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|
360 |
dpavlin |
6 |
res = 0; |
361 |
|
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if (!no_exceptions || (mem->dev_flags[i] & |
362 |
|
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MEM_READING_HAS_NO_SIDE_EFFECTS)) |
363 |
|
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res = mem->dev_f[i](cpu, mem, paddr, |
364 |
|
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data, len, writeflag, |
365 |
|
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mem->dev_extra[i]); |
366 |
dpavlin |
2 |
|
367 |
|
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#ifdef ENABLE_INSTRUCTION_DELAYS |
368 |
|
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if (res == 0) |
369 |
|
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res = -1; |
370 |
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|
371 |
|
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cpu->cd.mips.instruction_delay += |
372 |
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( (abs(res) - 1) * |
373 |
|
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cpu->cd.mips.cpu_type.instrs_per_cycle ); |
374 |
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|
#endif |
375 |
dpavlin |
6 |
|
376 |
|
|
#ifndef MEM_X86 |
377 |
dpavlin |
2 |
/* |
378 |
|
|
* If accessing the memory mapped device |
379 |
|
|
* failed, then return with a DBE exception. |
380 |
|
|
*/ |
381 |
dpavlin |
6 |
if (res <= 0 && !no_exceptions) { |
382 |
dpavlin |
2 |
debug("%s device '%s' addr %08lx " |
383 |
|
|
"failed\n", writeflag? |
384 |
|
|
"writing to" : "reading from", |
385 |
|
|
mem->dev_name[i], (long)paddr); |
386 |
|
|
#ifdef MEM_MIPS |
387 |
|
|
mips_cpu_exception(cpu, EXCEPTION_DBE, |
388 |
|
|
0, vaddr, 0, 0, 0, 0); |
389 |
|
|
#endif |
390 |
|
|
return MEMORY_ACCESS_FAILED; |
391 |
|
|
} |
392 |
dpavlin |
6 |
#endif |
393 |
dpavlin |
2 |
goto do_return_ok; |
394 |
|
|
} |
395 |
|
|
|
396 |
|
|
i ++; |
397 |
|
|
if (i == mem->n_mmapped_devices) |
398 |
|
|
i = 0; |
399 |
|
|
} while (i != start); |
400 |
|
|
} |
401 |
|
|
|
402 |
|
|
|
403 |
|
|
#ifdef MEM_MIPS |
404 |
|
|
/* |
405 |
|
|
* Data and instruction cache emulation: |
406 |
|
|
*/ |
407 |
|
|
|
408 |
|
|
switch (cpu->cd.mips.cpu_type.mmu_model) { |
409 |
|
|
case MMU3K: |
410 |
|
|
/* if not uncached addess (TODO: generalize this) */ |
411 |
|
|
if (!(cache_flags & PHYSICAL) && cache != CACHE_NONE && |
412 |
|
|
!((vaddr & 0xffffffffULL) >= 0xa0000000ULL && |
413 |
|
|
(vaddr & 0xffffffffULL) <= 0xbfffffffULL)) { |
414 |
|
|
if (memory_cache_R3000(cpu, cache, paddr, |
415 |
|
|
writeflag, len, data)) |
416 |
|
|
goto do_return_ok; |
417 |
|
|
} |
418 |
|
|
break; |
419 |
|
|
default: |
420 |
|
|
/* R4000 etc */ |
421 |
|
|
/* TODO */ |
422 |
|
|
; |
423 |
|
|
} |
424 |
|
|
#endif /* MEM_MIPS */ |
425 |
|
|
|
426 |
|
|
|
427 |
|
|
/* Outside of physical RAM? */ |
428 |
|
|
if (paddr >= mem->physical_max) { |
429 |
dpavlin |
6 |
#ifdef MEM_MIPS |
430 |
|
|
if ((paddr & 0xffffc00000ULL) == 0x1fc00000) { |
431 |
dpavlin |
2 |
/* Ok, this is PROM stuff */ |
432 |
|
|
} else if ((paddr & 0xfffff00000ULL) == 0x1ff00000) { |
433 |
|
|
/* Sprite reads from this area of memory... */ |
434 |
|
|
/* TODO: is this still correct? */ |
435 |
|
|
if (writeflag == MEM_READ) |
436 |
|
|
memset(data, 0, len); |
437 |
|
|
goto do_return_ok; |
438 |
dpavlin |
6 |
} else |
439 |
|
|
#endif /* MIPS */ |
440 |
|
|
{ |
441 |
|
|
if (paddr >= mem->physical_max) { |
442 |
dpavlin |
2 |
char *symbol; |
443 |
dpavlin |
12 |
uint64_t old_pc; |
444 |
|
|
uint64_t offset; |
445 |
|
|
|
446 |
dpavlin |
2 |
#ifdef MEM_MIPS |
447 |
dpavlin |
12 |
old_pc = cpu->cd.mips.pc_last; |
448 |
|
|
#else |
449 |
|
|
/* Default instruction size on most |
450 |
|
|
RISC archs is 32 bits: */ |
451 |
|
|
old_pc = cpu->pc - sizeof(uint32_t); |
452 |
dpavlin |
2 |
#endif |
453 |
dpavlin |
12 |
|
454 |
dpavlin |
6 |
/* This allows for example OS kernels to probe |
455 |
|
|
memory a few KBs past the end of memory, |
456 |
|
|
without giving too many warnings. */ |
457 |
dpavlin |
12 |
if (!quiet_mode && !no_exceptions && paddr >= |
458 |
dpavlin |
6 |
mem->physical_max + 0x40000) { |
459 |
dpavlin |
2 |
fatal("[ memory_rw(): writeflag=%i ", |
460 |
|
|
writeflag); |
461 |
|
|
if (writeflag) { |
462 |
|
|
unsigned int i; |
463 |
|
|
debug("data={", writeflag); |
464 |
|
|
if (len > 16) { |
465 |
|
|
int start2 = len-16; |
466 |
|
|
for (i=0; i<16; i++) |
467 |
|
|
debug("%s%02x", |
468 |
|
|
i?",":"", |
469 |
|
|
data[i]); |
470 |
|
|
debug(" .. "); |
471 |
|
|
if (start2 < 16) |
472 |
|
|
start2 = 16; |
473 |
|
|
for (i=start2; i<len; |
474 |
|
|
i++) |
475 |
|
|
debug("%s%02x", |
476 |
|
|
i?",":"", |
477 |
|
|
data[i]); |
478 |
|
|
} else |
479 |
|
|
for (i=0; i<len; i++) |
480 |
|
|
debug("%s%02x", |
481 |
|
|
i?",":"", |
482 |
|
|
data[i]); |
483 |
|
|
debug("}"); |
484 |
|
|
} |
485 |
dpavlin |
12 |
|
486 |
|
|
fatal(" paddr=0x%llx >= physical_max" |
487 |
|
|
"; pc=", (long long)paddr); |
488 |
|
|
if (cpu->is_32bit) |
489 |
|
|
fatal("0x%08x",(int)old_pc); |
490 |
|
|
else |
491 |
|
|
fatal("0x%016llx", |
492 |
|
|
(long long)old_pc); |
493 |
dpavlin |
2 |
symbol = get_symbol_name( |
494 |
|
|
&cpu->machine->symbol_context, |
495 |
dpavlin |
12 |
old_pc, &offset); |
496 |
|
|
fatal(" <%s> ]\n", |
497 |
|
|
symbol? symbol : " no symbol "); |
498 |
dpavlin |
2 |
} |
499 |
|
|
|
500 |
|
|
if (cpu->machine->single_step_on_bad_addr) { |
501 |
|
|
fatal("[ unimplemented access to " |
502 |
dpavlin |
12 |
"0x%llx, pc=0x",(long long)paddr); |
503 |
|
|
if (cpu->is_32bit) |
504 |
|
|
fatal("%08x ]\n", |
505 |
|
|
(int)old_pc); |
506 |
|
|
else |
507 |
|
|
fatal("%016llx ]\n", |
508 |
|
|
(long long)old_pc); |
509 |
dpavlin |
2 |
single_step = 1; |
510 |
|
|
} |
511 |
|
|
} |
512 |
|
|
|
513 |
|
|
if (writeflag == MEM_READ) { |
514 |
dpavlin |
6 |
#ifdef MEM_X86 |
515 |
|
|
/* Reading non-existant memory on x86: */ |
516 |
|
|
memset(data, 0xff, len); |
517 |
|
|
#else |
518 |
dpavlin |
2 |
/* Return all zeroes? (Or 0xff? TODO) */ |
519 |
|
|
memset(data, 0, len); |
520 |
dpavlin |
6 |
#endif |
521 |
dpavlin |
2 |
|
522 |
|
|
#ifdef MEM_MIPS |
523 |
|
|
/* |
524 |
|
|
* For real data/instruction accesses, cause |
525 |
|
|
* an exceptions on an illegal read: |
526 |
|
|
*/ |
527 |
|
|
if (cache != CACHE_NONE && cpu->machine-> |
528 |
dpavlin |
6 |
dbe_on_nonexistant_memaccess && |
529 |
|
|
!no_exceptions) { |
530 |
dpavlin |
2 |
if (paddr >= mem->physical_max && |
531 |
|
|
paddr < mem->physical_max+1048576) |
532 |
|
|
mips_cpu_exception(cpu, |
533 |
|
|
EXCEPTION_DBE, 0, vaddr, 0, |
534 |
|
|
0, 0, 0); |
535 |
|
|
} |
536 |
|
|
#endif /* MEM_MIPS */ |
537 |
|
|
} |
538 |
|
|
|
539 |
|
|
/* Hm? Shouldn't there be a DBE exception for |
540 |
|
|
invalid writes as well? TODO */ |
541 |
|
|
|
542 |
|
|
goto do_return_ok; |
543 |
|
|
} |
544 |
|
|
} |
545 |
|
|
|
546 |
|
|
#endif /* ifndef MEM_USERLAND */ |
547 |
|
|
|
548 |
|
|
|
549 |
|
|
/* |
550 |
|
|
* Uncached access: |
551 |
|
|
*/ |
552 |
|
|
memblock = memory_paddr_to_hostaddr(mem, paddr, writeflag); |
553 |
|
|
if (memblock == NULL) { |
554 |
|
|
if (writeflag == MEM_READ) |
555 |
|
|
memset(data, 0, len); |
556 |
|
|
goto do_return_ok; |
557 |
|
|
} |
558 |
|
|
|
559 |
|
|
offset = paddr & ((1 << BITS_PER_MEMBLOCK) - 1); |
560 |
|
|
|
561 |
dpavlin |
12 |
if (cpu->update_translation_table != NULL && !bintrans_device_danger) |
562 |
|
|
cpu->update_translation_table(cpu, vaddr & ~offset_mask, |
563 |
|
|
memblock + (offset & ~offset_mask), |
564 |
dpavlin |
2 |
#if 0 |
565 |
|
|
cache == CACHE_INSTRUCTION? |
566 |
|
|
(writeflag == MEM_WRITE? 1 : 0) |
567 |
|
|
: ok - 1, |
568 |
|
|
#else |
569 |
|
|
writeflag == MEM_WRITE? 1 : 0, |
570 |
|
|
#endif |
571 |
dpavlin |
12 |
paddr & ~offset_mask); |
572 |
dpavlin |
2 |
|
573 |
|
|
if (writeflag == MEM_WRITE) { |
574 |
dpavlin |
12 |
/* Ugly optimization, but it works: */ |
575 |
|
|
if (len == sizeof(uint32_t) && (offset & 3)==0 |
576 |
|
|
&& ((size_t)data&3)==0) |
577 |
dpavlin |
2 |
*(uint32_t *)(memblock + offset) = *(uint32_t *)data; |
578 |
|
|
else if (len == sizeof(uint8_t)) |
579 |
|
|
*(uint8_t *)(memblock + offset) = *(uint8_t *)data; |
580 |
|
|
else |
581 |
|
|
memcpy(memblock + offset, data, len); |
582 |
|
|
} else { |
583 |
dpavlin |
12 |
/* Ugly optimization, but it works: */ |
584 |
|
|
if (len == sizeof(uint32_t) && (offset & 3)==0 |
585 |
|
|
&& ((size_t)data&3)==0) |
586 |
dpavlin |
2 |
*(uint32_t *)data = *(uint32_t *)(memblock + offset); |
587 |
|
|
else if (len == sizeof(uint8_t)) |
588 |
|
|
*(uint8_t *)data = *(uint8_t *)(memblock + offset); |
589 |
|
|
else |
590 |
|
|
memcpy(data, memblock + offset, len); |
591 |
|
|
|
592 |
dpavlin |
6 |
#ifdef MEM_MIPS |
593 |
dpavlin |
2 |
if (cache == CACHE_INSTRUCTION) { |
594 |
|
|
cpu->cd.mips.pc_last_host_4k_page = memblock |
595 |
dpavlin |
12 |
+ (offset & ~offset_mask); |
596 |
dpavlin |
2 |
if (bintrans_cached) { |
597 |
|
|
cpu->cd.mips.pc_bintrans_host_4kpage = |
598 |
|
|
cpu->cd.mips.pc_last_host_4k_page; |
599 |
|
|
} |
600 |
|
|
} |
601 |
dpavlin |
6 |
#endif /* MIPS */ |
602 |
dpavlin |
2 |
} |
603 |
|
|
|
604 |
|
|
|
605 |
|
|
do_return_ok: |
606 |
|
|
return MEMORY_ACCESS_OK; |
607 |
|
|
} |
608 |
|
|
|