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/* GXemul: $Id: sh4_scireg.h,v 1.2 2007/04/13 16:07:26 debug Exp $ */ |
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/* $OpenBSD: scireg.h,v 1.1.1.1 2006/10/06 21:02:55 miod Exp $ */ |
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/* $NetBSD: scireg.h,v 1.8 2003/07/01 11:49:37 uwe Exp $ */ |
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|
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#ifndef SH4_SCIREG_H |
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#define SH4_SCIREG_H |
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|
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/* GXemul base address for SCI-connected devices: */ |
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#define SCI_DEVICE_BASE 0x81000000ULL |
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|
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|
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/*- |
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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/* |
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* Serial Communication Interface (SCI) |
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*/ |
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|
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#if 0 |
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!defined(SH4) |
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|
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/* SH3 definitions */ |
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|
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#define SHREG_SCSMR (*(volatile unsigned char *) 0xFFFFFE80) |
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#define SHREG_SCBRR (*(volatile unsigned char *) 0xFFFFFE82) |
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#define SHREG_SCSCR (*(volatile unsigned char *) 0xFFFFFE84) |
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#define SHREG_SCTDR (*(volatile unsigned char *) 0xFFFFFE86) |
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#define SHREG_SCSSR (*(volatile unsigned char *) 0xFFFFFE88) |
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#define SHREG_SCRDR (*(volatile unsigned char *) 0xFFFFFE8A) |
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#define SHREG_SCSPDR (*(volatile unsigned char *) 0xf4000136) |
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|
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#else |
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|
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/* SH4 definitions */ |
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|
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#define SHREG_SCSMR /* (*(volatile unsigned char *) */ 0xffe00000 |
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#define SHREG_SCBRR /* (*(volatile unsigned char *) */ 0xffe00004 |
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#define SHREG_SCSCR /* (*(volatile unsigned char *) */ 0xffe00008 |
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#define SHREG_SCTDR /* (*(volatile unsigned char *) */ 0xffe0000c |
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#define SHREG_SCSSR /* (*(volatile unsigned char *) */ 0xffe00010 |
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#define SHREG_SCRDR /* (*(volatile unsigned char *) */ 0xffe00014 |
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#define SHREG_SCSPTR /* (*(volatile unsigned char *) */ 0xffe0001c |
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|
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#endif |
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|
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#define SCSCR_TIE 0x80 /* Transmit Interrupt Enable */ |
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#define SCSCR_RIE 0x40 /* Receive Interrupt Enable */ |
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#define SCSCR_TE 0x20 /* Transmit Enable */ |
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#define SCSCR_RE 0x10 /* Receive Enable */ |
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#define SCSCR_MPIE 0x08 /* Multi Processor Interrupt Enable */ |
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#define SCSCR_TEIE 0x04 /* Transmit End Interrupt Enable */ |
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#define SCSCR_CKE1 0x02 /* ClocK Enable 1 */ |
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#define SCSCR_CKE0 0x01 /* ClocK Enable 0 */ |
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|
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#define SCSSR_TDRE 0x80 |
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#define SCSSR_RDRF 0x40 |
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#define SCSSR_ORER 0x20 |
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#define SCSSR_FER 0x10 |
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#define SCSSR_PER 0x08 |
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|
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#define SCSPTR_SPB1IO 0x08 |
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#define SCSPTR_SPB1DT 0x04 |
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#define SCSPTR_SPB0IO 0x02 |
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#define SCSPTR_SPB0DT 0x01 |
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|
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#if defined(SH3) |
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#define SCSPDR_SCP0DT 0x01 |
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#endif |
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|
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|
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#endif /* SH4_SCIREG_H */ |