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/* GXemul: $Id: rtl81x9reg.h,v 1.1 2007/04/21 02:36:23 debug Exp $ */ |
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/* $OpenBSD: rtl81x9reg.h,v 1.36 2006/12/12 10:24:38 reyk Exp $ */ |
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|
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#ifndef RTL81X9REG_H |
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#define RTL81X9REG_H |
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|
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/* |
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* Copyright (c) 1997, 1998 |
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by Bill Paul. |
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* 4. Neither the name of the author nor the names of any co-contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
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* THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* $FreeBSD: src/sys/pci/if_rlreg.h,v 1.14 1999/10/21 19:42:03 wpaul Exp $ |
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*/ |
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|
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/* |
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* RealTek 8129/8139 register offsets |
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*/ |
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#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ |
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#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ |
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#define RL_IDR2 0x0002 |
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#define RL_IDR3 0x0003 |
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#define RL_IDR4 0x0004 |
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#define RL_IDR5 0x0005 |
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/* 0006-0007 reserved */ |
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#define RL_MAR0 0x0008 /* Multicast hash table */ |
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#define RL_MAR1 0x0009 |
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#define RL_MAR2 0x000A |
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#define RL_MAR3 0x000B |
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#define RL_MAR4 0x000C |
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#define RL_MAR5 0x000D |
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#define RL_MAR6 0x000E |
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#define RL_MAR7 0x000F |
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|
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#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ |
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#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ |
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#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ |
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#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ |
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|
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#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ |
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#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ |
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#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ |
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#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ |
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|
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#define RL_RXADDR 0x0030 /* RX ring start address */ |
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#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ |
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#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ |
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#define RL_COMMAND 0x0037 /* command register */ |
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#define RL_CURRXADDR 0x0038 /* current address of packet read */ |
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#define RL_CURRXBUF 0x003A /* current RX buffer address */ |
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#define RL_IMR 0x003C /* interrupt mask register */ |
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#define RL_ISR 0x003E /* interrupt status register */ |
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#define RL_TXCFG 0x0040 /* transmit config */ |
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#define RL_RXCFG 0x0044 /* receive config */ |
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#define RL_TIMERCNT 0x0048 /* timer count register */ |
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#define RL_MISSEDPKT 0x004C /* missed packet counter */ |
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#define RL_EECMD 0x0050 /* EEPROM command register */ |
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#define RL_CFG0 0x0051 /* config register #0 */ |
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#define RL_CFG1 0x0052 /* config register #1 */ |
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/* 0053-0057 reserved */ |
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#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ |
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/* 0059-005A reserved */ |
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#define RL_MII 0x005A /* 8129 chip only */ |
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#define RL_HALTCLK 0x005B |
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#define RL_MULTIINTR 0x005C /* multiple interrupt */ |
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#define RL_PCIREV 0x005E /* PCI revision value */ |
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/* 005F reserved */ |
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#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ |
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|
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/* Direct PHY access registers only available on 8139 */ |
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#define RL_BMCR 0x0062 /* PHY basic mode control */ |
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#define RL_BMSR 0x0064 /* PHY basic mode status */ |
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#define RL_ANAR 0x0066 /* PHY autoneg advert */ |
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#define RL_LPAR 0x0068 /* PHY link partner ability */ |
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#define RL_ANER 0x006A /* PHY autoneg expansion */ |
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|
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#define RL_DISCCNT 0x006C /* disconnect counter */ |
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#define RL_FALSECAR 0x006E /* false carrier counter */ |
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#define RL_NWAYTST 0x0070 /* NWAY test register */ |
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#define RL_RX_ER 0x0072 /* RX_ER counter */ |
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#define RL_CSCFG 0x0074 /* CS configuration register */ |
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|
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/* |
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* When operating in special C+ mode, some of the registers in an |
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* 8139C+ chip have different definitions. These are also used for |
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* the 8169 gigE chip. |
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*/ |
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#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ |
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#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ |
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#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ |
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#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ |
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#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */ |
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#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */ |
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#define RL_CFG2 0x0053 |
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#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ |
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#define RL_TXSTART 0x00D9 /* 8 bits */ |
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#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ |
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#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ |
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#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ |
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#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ |
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|
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/* |
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* Registers specific to the 8169 gigE chip |
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*/ |
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#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ |
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#define RL_PHYAR 0x0060 |
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#define RL_TBICSR 0x0064 |
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#define RL_TBI_ANAR 0x0068 |
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#define RL_TBI_LPAR 0x006A |
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#define RL_GMEDIASTAT 0x006C /* 8 bits */ |
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#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ |
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#define RL_GTXSTART 0x0038 /* 16 bits */ |
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/* |
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* TX config register bits |
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*/ |
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#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ |
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#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ |
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#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ |
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#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ |
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#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ |
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#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ |
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#define RL_TXCFG_HWREV 0x7C800000 |
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|
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#define RL_LOOPTEST_OFF 0x00000000 |
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#define RL_LOOPTEST_ON 0x00020000 |
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#define RL_LOOPTEST_ON_CPLUS 0x00060000 |
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|
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/* Known revision codes. */ |
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|
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#define RL_HWREV_8169 0x00000000 |
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#define RL_HWREV_8110S 0x00800000 |
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#define RL_HWREV_8169S 0x04000000 |
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#define RL_HWREV_8169_8110SB 0x10000000 |
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#define RL_HWREV_8169_8110SC 0x18000000 |
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#define RL_HWREV_8168_SPIN1 0x30000000 |
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#define RL_HWREV_8100E_SPIN1 0x30800000 |
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#define RL_HWREV_8101E 0x34000000 |
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#define RL_HWREV_8168_SPIN2 0x38000000 |
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#define RL_HWREV_8100E_SPIN2 0x38800000 |
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#define RL_HWREV_8139 0x60000000 |
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#define RL_HWREV_8139A 0x70000000 |
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#define RL_HWREV_8139AG 0x70800000 |
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#define RL_HWREV_8139B 0x78000000 |
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#define RL_HWREV_8130 0x7C000000 |
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#define RL_HWREV_8139C 0x74000000 |
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#define RL_HWREV_8139D 0x74400000 |
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#define RL_HWREV_8139CPLUS 0x74800000 |
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#define RL_HWREV_8101 0x74c00000 |
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#define RL_HWREV_8100 0x78800000 |
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|
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#define RL_TXDMA_16BYTES 0x00000000 |
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#define RL_TXDMA_32BYTES 0x00000100 |
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#define RL_TXDMA_64BYTES 0x00000200 |
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#define RL_TXDMA_128BYTES 0x00000300 |
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#define RL_TXDMA_256BYTES 0x00000400 |
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#define RL_TXDMA_512BYTES 0x00000500 |
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#define RL_TXDMA_1024BYTES 0x00000600 |
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#define RL_TXDMA_2048BYTES 0x00000700 |
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|
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/* |
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* Transmit descriptor status register bits. |
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*/ |
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#define RL_TXSTAT_LENMASK 0x00001FFF |
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#define RL_TXSTAT_OWN 0x00002000 |
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#define RL_TXSTAT_TX_UNDERRUN 0x00004000 |
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#define RL_TXSTAT_TX_OK 0x00008000 |
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#define RL_TXSTAT_EARLY_THRESH 0x003F0000 |
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#define RL_TXSTAT_COLLCNT 0x0F000000 |
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#define RL_TXSTAT_CARR_HBEAT 0x10000000 |
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#define RL_TXSTAT_OUTOFWIN 0x20000000 |
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#define RL_TXSTAT_TXABRT 0x40000000 |
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#define RL_TXSTAT_CARRLOSS 0x80000000 |
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|
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/* |
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* Interrupt status register bits. |
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*/ |
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#define RL_ISR_RX_OK 0x0001 |
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#define RL_ISR_RX_ERR 0x0002 |
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#define RL_ISR_TX_OK 0x0004 |
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#define RL_ISR_TX_ERR 0x0008 |
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#define RL_ISR_RX_OVERRUN 0x0010 |
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#define RL_ISR_PKT_UNDERRUN 0x0020 |
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#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ |
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#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ |
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#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ |
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#define RL_ISR_SWI 0x0100 /* C+ only */ |
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#define RL_ISR_CABLE_LEN_CHGD 0x2000 |
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#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ |
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#define RL_ISR_TIMEOUT_EXPIRED 0x4000 |
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#define RL_ISR_SYSTEM_ERR 0x8000 |
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|
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#define RL_INTRS \ |
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(RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ |
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RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ |
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RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) |
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|
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#define RL_INTRS_CPLUS \ |
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(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ |
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RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ |
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RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) |
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|
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|
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/* |
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* Media status register. (8139 only) |
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*/ |
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#define RL_MEDIASTAT_RXPAUSE 0x01 |
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#define RL_MEDIASTAT_TXPAUSE 0x02 |
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#define RL_MEDIASTAT_LINK 0x04 |
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#define RL_MEDIASTAT_SPEED10 0x08 |
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#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ |
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#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ |
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|
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/* |
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* Receive config register. |
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*/ |
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#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ |
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#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ |
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#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ |
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#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ |
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#define RL_RXCFG_RX_RUNT 0x00000010 |
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#define RL_RXCFG_RX_ERRPKT 0x00000020 |
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#define RL_RXCFG_WRAP 0x00000080 |
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#define RL_RXCFG_MAXDMA 0x00000700 |
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#define RL_RXCFG_BURSZ 0x00001800 |
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#define RL_RXCFG_FIFOTHRESH 0x0000E000 |
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#define RL_RXCFG_EARLYTHRESH 0x07000000 |
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|
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#define RL_RXDMA_16BYTES 0x00000000 |
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#define RL_RXDMA_32BYTES 0x00000100 |
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#define RL_RXDMA_64BYTES 0x00000200 |
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#define RL_RXDMA_128BYTES 0x00000300 |
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#define RL_RXDMA_256BYTES 0x00000400 |
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#define RL_RXDMA_512BYTES 0x00000500 |
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#define RL_RXDMA_1024BYTES 0x00000600 |
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#define RL_RXDMA_UNLIMITED 0x00000700 |
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|
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#define RL_RXBUF_8 0x00000000 |
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#define RL_RXBUF_16 0x00000800 |
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#define RL_RXBUF_32 0x00001000 |
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#define RL_RXBUF_64 0x00001800 |
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|
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#define RL_RXFIFO_16BYTES 0x00000000 |
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#define RL_RXFIFO_32BYTES 0x00002000 |
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#define RL_RXFIFO_64BYTES 0x00004000 |
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#define RL_RXFIFO_128BYTES 0x00006000 |
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#define RL_RXFIFO_256BYTES 0x00008000 |
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#define RL_RXFIFO_512BYTES 0x0000A000 |
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#define RL_RXFIFO_1024BYTES 0x0000C000 |
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#define RL_RXFIFO_NOTHRESH 0x0000E000 |
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|
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/* |
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* Bits in RX status header (included with RX'ed packet |
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* in ring buffer). |
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*/ |
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#define RL_RXSTAT_RXOK 0x00000001 |
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#define RL_RXSTAT_ALIGNERR 0x00000002 |
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#define RL_RXSTAT_CRCERR 0x00000004 |
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#define RL_RXSTAT_GIANT 0x00000008 |
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#define RL_RXSTAT_RUNT 0x00000010 |
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#define RL_RXSTAT_BADSYM 0x00000020 |
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#define RL_RXSTAT_BROAD 0x00002000 |
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#define RL_RXSTAT_INDIV 0x00004000 |
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#define RL_RXSTAT_MULTI 0x00008000 |
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#define RL_RXSTAT_LENMASK 0xFFFF0000 |
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|
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#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ |
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/* |
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* Command register. |
294 |
*/ |
295 |
#define RL_CMD_EMPTY_RXBUF 0x0001 |
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#define RL_CMD_TX_ENB 0x0004 |
297 |
#define RL_CMD_RX_ENB 0x0008 |
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#define RL_CMD_RESET 0x0010 |
299 |
|
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/* |
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* EEPROM control register |
302 |
*/ |
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#define RL_EE_DATAOUT 0x01 /* Data out */ |
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#define RL_EE_DATAIN 0x02 /* Data in */ |
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#define RL_EE_CLK 0x04 /* clock */ |
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#define RL_EE_SEL 0x08 /* chip select */ |
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#define RL_EE_MODE (0x40|0x80) |
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|
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#define RL_EEMODE_OFF 0x00 |
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#define RL_EEMODE_AUTOLOAD 0x40 |
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#define RL_EEMODE_PROGRAM 0x80 |
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#define RL_EEMODE_WRITECFG (0x80|0x40) |
313 |
|
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/* 9346/9356 EEPROM commands */ |
315 |
|
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#define RL_9346_WRITE 0x5 |
317 |
#define RL_9346_READ 0x6 |
318 |
#define RL_9346_ERASE 0x7 |
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#define RL_9346_EWEN 0x4 |
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#define RL_9346_EWEN_ADDR 0x30 |
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#define RL_9456_EWDS 0x4 |
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#define RL_9346_EWDS_ADDR 0x00 |
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|
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#define RL_EECMD_WRITE 0x5 /* 0101b */ |
325 |
#define RL_EECMD_READ 0x6 /* 0110b */ |
326 |
#define RL_EECMD_ERASE 0x7 /* 0111b */ |
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#define RL_EECMD_LEN 4 |
328 |
|
329 |
#define RL_EEADDR_LEN0 6 /* 9346 */ |
330 |
#define RL_EEADDR_LEN1 8 /* 9356 */ |
331 |
|
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#define RL_EECMD_READ_6BIT 0x180 /* XXX */ |
333 |
#define RL_EECMD_READ_8BIT 0x600 /* EECMD_READ above maybe wrong? */ |
334 |
|
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#define RL_EE_ID 0x00 |
336 |
#define RL_EE_PCI_VID 0x01 |
337 |
#define RL_EE_PCI_DID 0x02 |
338 |
/* Location of station address inside EEPROM */ |
339 |
#define RL_EE_EADDR 0x07 |
340 |
|
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/* |
342 |
* MII register (8129 only) |
343 |
*/ |
344 |
#define RL_MII_CLK 0x01 |
345 |
#define RL_MII_DATAIN 0x02 |
346 |
#define RL_MII_DATAOUT 0x04 |
347 |
#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ |
348 |
|
349 |
/* |
350 |
* Config 0 register |
351 |
*/ |
352 |
#define RL_CFG0_ROM0 0x01 |
353 |
#define RL_CFG0_ROM1 0x02 |
354 |
#define RL_CFG0_ROM2 0x04 |
355 |
#define RL_CFG0_PL0 0x08 |
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#define RL_CFG0_PL1 0x10 |
357 |
#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ |
358 |
#define RL_CFG0_PCS 0x40 |
359 |
#define RL_CFG0_SCR 0x80 |
360 |
|
361 |
/* |
362 |
* Config 1 register |
363 |
*/ |
364 |
#define RL_CFG1_PWRDWN 0x01 |
365 |
#define RL_CFG1_SLEEP 0x02 |
366 |
#define RL_CFG1_IOMAP 0x04 |
367 |
#define RL_CFG1_MEMMAP 0x08 |
368 |
#define RL_CFG1_RSVD 0x10 |
369 |
#define RL_CFG1_DRVLOAD 0x20 |
370 |
#define RL_CFG1_LED0 0x40 |
371 |
#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ |
372 |
#define RL_CFG1_LED1 0x80 |
373 |
|
374 |
/* |
375 |
* 8139C+ register definitions |
376 |
*/ |
377 |
|
378 |
/* RL_DUMPSTATS_LO register */ |
379 |
|
380 |
#define RL_DUMPSTATS_START 0x00000008 |
381 |
|
382 |
/* Transmit start register */ |
383 |
|
384 |
#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ |
385 |
#define RL_TXSTART_START 0x40 /* start normal queue transmit */ |
386 |
#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ |
387 |
|
388 |
/* |
389 |
* Config 2 register, 8139C+/8169/8169S/8110S only |
390 |
*/ |
391 |
#define RL_CFG2_BUSFREQ 0x07 |
392 |
#define RL_CFG2_BUSWIDTH 0x08 |
393 |
#define RL_CFG2_AUXPWRSTS 0x10 |
394 |
|
395 |
#define RL_BUSFREQ_33MHZ 0x00 |
396 |
#define RL_BUSFREQ_66MHZ 0x01 |
397 |
|
398 |
#define RL_BUSWIDTH_32BITS 0x00 |
399 |
#define RL_BUSWIDTH_64BITS 0x08 |
400 |
|
401 |
/* C+ mode command register */ |
402 |
|
403 |
#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ |
404 |
#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ |
405 |
#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ |
406 |
#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ |
407 |
#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ |
408 |
#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ |
409 |
|
410 |
/* C+ early transmit threshold */ |
411 |
|
412 |
#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ |
413 |
|
414 |
/* |
415 |
* Gigabit PHY access register (8169 only) |
416 |
*/ |
417 |
|
418 |
#define RL_PHYAR_PHYDATA 0x0000FFFF |
419 |
#define RL_PHYAR_PHYREG 0x001F0000 |
420 |
#define RL_PHYAR_BUSY 0x80000000 |
421 |
|
422 |
/* |
423 |
* Gigabit media status (8169 only) |
424 |
*/ |
425 |
#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ |
426 |
#define RL_GMEDIASTAT_LINK 0x02 /* link up */ |
427 |
#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ |
428 |
#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ |
429 |
#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ |
430 |
#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ |
431 |
#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ |
432 |
#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ |
433 |
|
434 |
/* |
435 |
* The RealTek doesn't use a fragment-based descriptor mechanism. |
436 |
* Instead, there are only four register sets, each or which represents |
437 |
* one 'descriptor.' Basically, each TX descriptor is just a contiguous |
438 |
* packet buffer (32-bit aligned!) and we place the buffer addresses in |
439 |
* the registers so the chip knows where they are. |
440 |
* |
441 |
* We can sort of kludge together the same kind of buffer management |
442 |
* used in previous drivers, but we have to do buffer copies almost all |
443 |
* the time, so it doesn't really buy us much. |
444 |
* |
445 |
* For reception, there's just one large buffer where the chip stores |
446 |
* all received packets. |
447 |
*/ |
448 |
|
449 |
#define RL_RX_BUF_SZ RL_RXBUF_64 |
450 |
#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) |
451 |
#define RL_TX_LIST_CNT 4 |
452 |
#define RL_MIN_FRAMELEN 60 |
453 |
#define RL_TXTHRESH(x) ((x) << 11) |
454 |
#define RL_TX_THRESH_INIT 96 |
455 |
#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES |
456 |
#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED |
457 |
#define RL_TX_MAXDMA RL_TXDMA_2048BYTES |
458 |
|
459 |
#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) |
460 |
#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) |
461 |
|
462 |
#if 0 |
463 |
struct rl_chain_data { |
464 |
u_int16_t cur_rx; |
465 |
caddr_t rl_rx_buf; |
466 |
caddr_t rl_rx_buf_ptr; |
467 |
bus_addr_t rl_rx_buf_pa; |
468 |
|
469 |
struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; |
470 |
bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; |
471 |
u_int8_t last_tx; |
472 |
u_int8_t cur_tx; |
473 |
}; |
474 |
#endif |
475 |
|
476 |
|
477 |
/* |
478 |
* The 8139C+ and 8160 gigE chips support descriptor-based TX |
479 |
* and RX. In fact, they even support TCP large send. Descriptors |
480 |
* must be allocated in contiguous blocks that are aligned on a |
481 |
* 256-byte boundary. The rings can hold a maximum of 64 descriptors. |
482 |
*/ |
483 |
|
484 |
/* |
485 |
* RX/TX descriptor definition. When large send mode is enabled, the |
486 |
* lower 11 bits of the TX rl_cmd word are used to hold the MSS, and |
487 |
* the checksum offload bits are disabled. The structure layout is |
488 |
* the same for RX and TX descriptors |
489 |
*/ |
490 |
|
491 |
struct rl_desc { |
492 |
volatile u_int32_t rl_cmdstat; |
493 |
volatile u_int32_t rl_vlanctl; |
494 |
volatile u_int32_t rl_bufaddr_lo; |
495 |
volatile u_int32_t rl_bufaddr_hi; |
496 |
}; |
497 |
|
498 |
#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF |
499 |
#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ |
500 |
#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ |
501 |
#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ |
502 |
#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ |
503 |
#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ |
504 |
#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ |
505 |
#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ |
506 |
#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ |
507 |
#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ |
508 |
|
509 |
#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ |
510 |
#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ |
511 |
|
512 |
/* |
513 |
* Error bits are valid only on the last descriptor of a frame |
514 |
* (i.e. RL_TDESC_CMD_EOF == 1) |
515 |
*/ |
516 |
|
517 |
#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ |
518 |
#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ |
519 |
#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ |
520 |
#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ |
521 |
#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ |
522 |
#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ |
523 |
#define RL_TDESC_STAT_OWN 0x80000000 |
524 |
|
525 |
/* |
526 |
* RX descriptor cmd/vlan definitions |
527 |
*/ |
528 |
|
529 |
#define RL_RDESC_CMD_EOR 0x40000000 |
530 |
#define RL_RDESC_CMD_OWN 0x80000000 |
531 |
#define RL_RDESC_CMD_BUFLEN 0x00001FFF |
532 |
|
533 |
#define RL_RDESC_STAT_OWN 0x80000000 |
534 |
#define RL_RDESC_STAT_EOR 0x40000000 |
535 |
#define RL_RDESC_STAT_SOF 0x20000000 |
536 |
#define RL_RDESC_STAT_EOF 0x10000000 |
537 |
#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ |
538 |
#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ |
539 |
#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ |
540 |
#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ |
541 |
#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ |
542 |
#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ |
543 |
#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ |
544 |
#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ |
545 |
#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ |
546 |
#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ |
547 |
#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ |
548 |
#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ |
549 |
#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ |
550 |
#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ |
551 |
#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ |
552 |
#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ |
553 |
#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ |
554 |
RL_RDESC_STAT_CRCERR) |
555 |
|
556 |
#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available |
557 |
(rl_vlandata valid)*/ |
558 |
#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ |
559 |
|
560 |
#define RL_PROTOID_NONIP 0x00000000 |
561 |
#define RL_PROTOID_TCPIP 0x00010000 |
562 |
#define RL_PROTOID_UDPIP 0x00020000 |
563 |
#define RL_PROTOID_IP 0x00030000 |
564 |
#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ |
565 |
RL_PROTOID_TCPIP) |
566 |
#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ |
567 |
RL_PROTOID_UDPIP) |
568 |
|
569 |
/* |
570 |
* Statistics counter structure (8139C+ and 8169 only) |
571 |
*/ |
572 |
struct rl_stats { |
573 |
u_int32_t rl_tx_pkts_lo; |
574 |
u_int32_t rl_tx_pkts_hi; |
575 |
u_int32_t rl_tx_errs_lo; |
576 |
u_int32_t rl_tx_errs_hi; |
577 |
u_int32_t rl_tx_errs; |
578 |
u_int16_t rl_missed_pkts; |
579 |
u_int16_t rl_rx_framealign_errs; |
580 |
u_int32_t rl_tx_onecoll; |
581 |
u_int32_t rl_tx_multicolls; |
582 |
u_int32_t rl_rx_ucasts_hi; |
583 |
u_int32_t rl_rx_ucasts_lo; |
584 |
u_int32_t rl_rx_bcasts_lo; |
585 |
u_int32_t rl_rx_bcasts_hi; |
586 |
u_int32_t rl_rx_mcasts; |
587 |
u_int16_t rl_tx_aborts; |
588 |
u_int16_t rl_rx_underruns; |
589 |
}; |
590 |
|
591 |
#define RL_RX_DESC_CNT 64 |
592 |
#define RL_TX_DESC_CNT_8139 64 |
593 |
#define RL_TX_DESC_CNT_8169 1024 |
594 |
|
595 |
#define RL_TX_QLEN 64 |
596 |
|
597 |
#define RL_NTXDESC_RSVD 4 |
598 |
|
599 |
#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) |
600 |
#define RL_RING_ALIGN 256 |
601 |
#define RL_PKTSZ(x) ((x)/* >> 3*/) |
602 |
#ifdef __STRICT_ALIGNMENT |
603 |
#define RE_ETHER_ALIGN 2 |
604 |
#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) |
605 |
#else |
606 |
#define RE_ETHER_ALIGN 0 |
607 |
#define RE_RX_DESC_BUFLEN MCLBYTES |
608 |
#endif |
609 |
|
610 |
#define RL_TX_DESC_CNT(sc) \ |
611 |
((sc)->rl_ldata.rl_tx_desc_cnt) |
612 |
#define RL_TX_LIST_SZ(sc) \ |
613 |
(RL_TX_DESC_CNT(sc) * sizeof(struct rl_desc)) |
614 |
#define RL_NEXT_TX_DESC(sc, x) \ |
615 |
(((x) + 1) % RL_TX_DESC_CNT(sc)) |
616 |
#define RL_NEXT_RX_DESC(sc, x) \ |
617 |
(((x) + 1) % RL_RX_DESC_CNT) |
618 |
#define RL_NEXT_TXQ(sc, x) \ |
619 |
(((x) + 1) % RL_TX_QLEN) |
620 |
|
621 |
#define RL_TXDESCSYNC(sc, idx, ops) \ |
622 |
bus_dmamap_sync((sc)->sc_dmat, \ |
623 |
(sc)->rl_ldata.rl_tx_list_map, \ |
624 |
sizeof(struct rl_desc) * (idx), \ |
625 |
sizeof(struct rl_desc), \ |
626 |
(ops)) |
627 |
#define RL_RXDESCSYNC(sc, idx, ops) \ |
628 |
bus_dmamap_sync((sc)->sc_dmat, \ |
629 |
(sc)->rl_ldata.rl_rx_list_map, \ |
630 |
sizeof(struct rl_desc) * (idx), \ |
631 |
sizeof(struct rl_desc), \ |
632 |
(ops)) |
633 |
|
634 |
#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) |
635 |
#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) |
636 |
|
637 |
/* see comment in dev/ic/re.c */ |
638 |
#define RL_JUMBO_FRAMELEN 7440 |
639 |
#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) |
640 |
|
641 |
#define MAX_NUM_MULTICAST_ADDRESSES 128 |
642 |
|
643 |
#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) |
644 |
#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) |
645 |
#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) |
646 |
#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) |
647 |
#define RL_CUR_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) |
648 |
#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) |
649 |
#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) |
650 |
#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) |
651 |
#define RL_LAST_TXMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) |
652 |
|
653 |
struct rl_type { |
654 |
u_int16_t rl_vid; |
655 |
u_int16_t rl_did; |
656 |
}; |
657 |
|
658 |
struct rl_mii_frame { |
659 |
u_int8_t mii_stdelim; |
660 |
u_int8_t mii_opcode; |
661 |
u_int8_t mii_phyaddr; |
662 |
u_int8_t mii_regaddr; |
663 |
u_int8_t mii_turnaround; |
664 |
u_int16_t mii_data; |
665 |
}; |
666 |
|
667 |
/* |
668 |
* MII constants |
669 |
*/ |
670 |
#define RL_MII_STARTDELIM 0x01 |
671 |
#define RL_MII_READOP 0x02 |
672 |
#define RL_MII_WRITEOP 0x01 |
673 |
#define RL_MII_TURNAROUND 0x02 |
674 |
|
675 |
#define RL_UNKNOWN 0 |
676 |
#define RL_8129 1 |
677 |
#define RL_8139 2 |
678 |
#define RL_8139CPLUS 3 |
679 |
#define RL_8169 4 |
680 |
|
681 |
#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ |
682 |
(x)->rl_type == RL_8169) |
683 |
|
684 |
#if 0 |
685 |
struct rl_rxsoft { |
686 |
struct mbuf *rxs_mbuf; |
687 |
bus_dmamap_t rxs_dmamap; |
688 |
}; |
689 |
|
690 |
struct rl_txq { |
691 |
struct mbuf *txq_mbuf; |
692 |
bus_dmamap_t txq_dmamap; |
693 |
int txq_descidx; |
694 |
int txq_nsegs; |
695 |
}; |
696 |
|
697 |
struct rl_list_data { |
698 |
struct rl_txq rl_txq[RL_TX_QLEN]; |
699 |
int rl_txq_considx; |
700 |
int rl_txq_prodidx; |
701 |
|
702 |
bus_dmamap_t rl_tx_list_map; |
703 |
struct rl_desc *rl_tx_list; |
704 |
int rl_tx_free; /* # of free descriptors */ |
705 |
int rl_tx_nextfree; /* next descriptor to use */ |
706 |
int rl_tx_desc_cnt; /* # of descriptors */ |
707 |
bus_dma_segment_t rl_tx_listseg; |
708 |
int rl_tx_listnseg; |
709 |
|
710 |
struct rl_rxsoft rl_rxsoft[RL_RX_DESC_CNT]; |
711 |
bus_dmamap_t rl_rx_list_map; |
712 |
struct rl_desc *rl_rx_list; |
713 |
int rl_rx_prodidx; |
714 |
bus_dma_segment_t rl_rx_listseg; |
715 |
int rl_rx_listnseg; |
716 |
}; |
717 |
|
718 |
struct rl_softc { |
719 |
struct device sc_dev; /* us, as a device */ |
720 |
void * sc_ih; /* interrupt vectoring */ |
721 |
bus_space_handle_t rl_bhandle; /* bus space handle */ |
722 |
bus_space_tag_t rl_btag; /* bus space tag */ |
723 |
bus_dma_tag_t sc_dmat; |
724 |
bus_dma_segment_t sc_rx_seg; |
725 |
bus_dmamap_t sc_rx_dmamap; |
726 |
struct arpcom sc_arpcom; /* interface info */ |
727 |
struct mii_data sc_mii; /* MII information */ |
728 |
u_int8_t rl_type; |
729 |
int rl_eecmd_read; |
730 |
int rl_eewidth; |
731 |
void *sc_sdhook; /* shutdownhook */ |
732 |
void *sc_pwrhook; |
733 |
int rl_txthresh; |
734 |
int sc_flags; /* misc flags */ |
735 |
struct rl_chain_data rl_cdata; |
736 |
struct timeout sc_tick_tmo; |
737 |
int if_flags; |
738 |
|
739 |
struct rl_list_data rl_ldata; |
740 |
struct mbuf *rl_head; |
741 |
struct mbuf *rl_tail; |
742 |
u_int32_t rl_rxlenmask; |
743 |
int rl_testmode; |
744 |
struct timeout timer_handle; |
745 |
|
746 |
int rl_txstart; |
747 |
int rl_link; |
748 |
}; |
749 |
#endif |
750 |
|
751 |
/* |
752 |
* re(4) hardware ip4csum-tx could be mangled with 28 byte or less IP packets |
753 |
*/ |
754 |
#define RL_IP4CSUMTX_MINLEN 28 |
755 |
#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) |
756 |
/* |
757 |
* XXX |
758 |
* We are allocating pad DMA buffer after RX DMA descs for now |
759 |
* because RL_TX_LIST_SZ(sc) always occupies whole page but |
760 |
* RL_RX_LIST_SZ is less than PAGE_SIZE so there is some unused region. |
761 |
*/ |
762 |
#define RL_RX_DMAMEM_SZ (RL_RX_LIST_SZ + RL_IP4CSUMTX_PADLEN) |
763 |
#define RL_TXPADOFF RL_RX_LIST_SZ |
764 |
#define RL_TXPADDADDR(sc) \ |
765 |
((sc)->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr + RL_TXPADOFF) |
766 |
|
767 |
|
768 |
#define RL_ATTACHED 0x00000001 /* attach has succeeded */ |
769 |
#define RL_ENABLED 0x00000002 /* chip is enabled */ |
770 |
#define RL_IS_ENABLED(sc) ((sc)->sc_flags & RL_ENABLED) |
771 |
|
772 |
/* |
773 |
* register space access macros |
774 |
*/ |
775 |
#define CSR_WRITE_RAW_4(sc, csr, val) \ |
776 |
bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4) |
777 |
#define CSR_WRITE_4(sc, csr, val) \ |
778 |
bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val) |
779 |
#define CSR_WRITE_2(sc, csr, val) \ |
780 |
bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val) |
781 |
#define CSR_WRITE_1(sc, csr, val) \ |
782 |
bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val) |
783 |
|
784 |
#define CSR_READ_4(sc, csr) \ |
785 |
bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr) |
786 |
#define CSR_READ_2(sc, csr) \ |
787 |
bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr) |
788 |
#define CSR_READ_1(sc, csr) \ |
789 |
bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr) |
790 |
|
791 |
#define CSR_SETBIT_1(sc, offset, val) \ |
792 |
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) |
793 |
|
794 |
#define CSR_CLRBIT_1(sc, offset, val) \ |
795 |
CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) |
796 |
|
797 |
#define CSR_SETBIT_2(sc, offset, val) \ |
798 |
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) |
799 |
|
800 |
#define CSR_CLRBIT_2(sc, offset, val) \ |
801 |
CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) |
802 |
|
803 |
#define CSR_SETBIT_4(sc, offset, val) \ |
804 |
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) |
805 |
|
806 |
#define CSR_CLRBIT_4(sc, offset, val) \ |
807 |
CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) |
808 |
|
809 |
#define RL_TIMEOUT 1000 |
810 |
|
811 |
/* |
812 |
* General constants that are fun to know. |
813 |
* |
814 |
* RealTek PCI vendor ID |
815 |
*/ |
816 |
#define RT_VENDORID 0x10EC |
817 |
|
818 |
/* |
819 |
* RealTek chip device IDs. |
820 |
*/ |
821 |
#define RT_DEVICEID_8129 0x8129 |
822 |
#define RT_DEVICEID_8101E 0x8136 |
823 |
#define RT_DEVICEID_8138 0x8138 |
824 |
#define RT_DEVICEID_8139 0x8139 |
825 |
#define RT_DEVICEID_8169SC 0x8167 |
826 |
#define RT_DEVICEID_8168 0x8168 |
827 |
#define RT_DEVICEID_8169 0x8169 |
828 |
#define RT_DEVICEID_8100 0x8100 |
829 |
|
830 |
/* |
831 |
* Accton PCI vendor ID |
832 |
*/ |
833 |
#define ACCTON_VENDORID 0x1113 |
834 |
|
835 |
/* |
836 |
* Accton MPX 5030/5038 device ID. |
837 |
*/ |
838 |
#define ACCTON_DEVICEID_5030 0x1211 |
839 |
|
840 |
/* |
841 |
* Delta Electronics Vendor ID. |
842 |
*/ |
843 |
#define DELTA_VENDORID 0x1500 |
844 |
|
845 |
/* |
846 |
* Delta device IDs. |
847 |
*/ |
848 |
#define DELTA_DEVICEID_8139 0x1360 |
849 |
|
850 |
/* |
851 |
* Addtron vendor ID. |
852 |
*/ |
853 |
#define ADDTRON_VENDORID 0x4033 |
854 |
|
855 |
/* |
856 |
* Addtron device IDs. |
857 |
*/ |
858 |
#define ADDTRON_DEVICEID_8139 0x1360 |
859 |
|
860 |
/* D-Link Vendor ID */ |
861 |
#define DLINK_VENDORID 0x1186 |
862 |
|
863 |
/* D-Link device IDs */ |
864 |
#define DLINK_DEVICEID_8139 0x1300 |
865 |
#define DLINK_DEVICEID_8139_2 0x1340 |
866 |
|
867 |
/* Abocom device IDs */ |
868 |
#define ABOCOM_DEVICEID_8139 0xab06 |
869 |
|
870 |
/* |
871 |
* PCI low memory base and low I/O base register, and |
872 |
* other PCI registers. Note: some are only available on |
873 |
* the 3c905B, in particular those that related to power management. |
874 |
*/ |
875 |
|
876 |
#define RL_PCI_VENDOR_ID 0x00 |
877 |
#define RL_PCI_DEVICE_ID 0x02 |
878 |
#define RL_PCI_COMMAND 0x04 |
879 |
#define RL_PCI_STATUS 0x06 |
880 |
#define RL_PCI_CLASSCODE 0x09 |
881 |
#define RL_PCI_LATENCY_TIMER 0x0D |
882 |
#define RL_PCI_HEADER_TYPE 0x0E |
883 |
#define RL_PCI_LOIO 0x10 |
884 |
#define RL_PCI_LOMEM 0x14 |
885 |
#define RL_PCI_BIOSROM 0x30 |
886 |
#define RL_PCI_INTLINE 0x3C |
887 |
#define RL_PCI_INTPIN 0x3D |
888 |
#define RL_PCI_MINGNT 0x3E |
889 |
#define RL_PCI_MINLAT 0x0F |
890 |
#define RL_PCI_RESETOPT 0x48 |
891 |
#define RL_PCI_EEPROM_DATA 0x4C |
892 |
|
893 |
#define RL_PCI_CAPID 0x50 /* 8 bits */ |
894 |
#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ |
895 |
#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ |
896 |
#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ |
897 |
|
898 |
#define RL_PSTATE_MASK 0x0003 |
899 |
#define RL_PSTATE_D0 0x0000 |
900 |
#define RL_PSTATE_D1 0x0002 |
901 |
#define RL_PSTATE_D2 0x0002 |
902 |
#define RL_PSTATE_D3 0x0003 |
903 |
#define RL_PME_EN 0x0010 |
904 |
#define RL_PME_STATUS 0x8000 |
905 |
|
906 |
#if 0 |
907 |
extern int rl_attach(struct rl_softc *); |
908 |
extern int rl_detach(struct rl_softc *); |
909 |
extern int rl_intr(void *); |
910 |
extern void rl_setmulti(struct rl_softc *); |
911 |
#endif |
912 |
|
913 |
#endif /* RTL81X9REG_H */ |