/[gxemul]/trunk/src/include/pcireg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 19 by dpavlin, Mon Oct 8 16:18:00 2007 UTC revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC
# Line 1  Line 1 
1  /*  gxemul: $Id: pcireg.h,v 1.4 2005/03/05 12:34:03 debug Exp $  */  /*  gxemul: $Id: pcireg.h,v 1.6 2005/11/17 13:53:43 debug Exp $  */
2  /*      $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $     */  /*      $NetBSD: pcireg.h,v 1.37 2002/03/22 20:03:20 drochner Exp $     */
3    
4  #ifndef _DEV_PCI_PCIREG_H_  #ifndef _DEV_PCI_PCIREG_H_
# Line 71  typedef u_int16_t pci_product_id_t; Line 71  typedef u_int16_t pci_product_id_t;
71              (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)              (((id) >> PCI_PRODUCT_SHIFT) & PCI_PRODUCT_MASK)
72    
73  #define PCI_ID_CODE(vid,pid)                                    \  #define PCI_ID_CODE(vid,pid)                                    \
74          ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) |      \      ((((vid) & PCI_VENDOR_MASK) << PCI_VENDOR_SHIFT) |          \
75           (((pid) & PCI_PRODUCT_MASK) << PCI_PRODUCT_SHIFT))     \       (((uint32_t)((pid) & PCI_PRODUCT_MASK)) << PCI_PRODUCT_SHIFT))
76    
77  /*  /*
78   * Command and status register.   * Command and status register.
# Line 85  typedef u_int16_t pci_product_id_t; Line 85  typedef u_int16_t pci_product_id_t;
85    
86  #define PCI_COMMAND_STATUS_CODE(cmd,stat)                       \  #define PCI_COMMAND_STATUS_CODE(cmd,stat)                       \
87          ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) |    \          ((((cmd) & PCI_COMMAND_MASK) >> PCI_COMMAND_SHIFT) |    \
88           (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT))      \           (((stat) & PCI_STATUS_MASK) >> PCI_STATUS_SHIFT))
89    
90  #define PCI_COMMAND_IO_ENABLE                   0x00000001  #define PCI_COMMAND_IO_ENABLE                   0x00000001
91  #define PCI_COMMAND_MEM_ENABLE                  0x00000002  #define PCI_COMMAND_MEM_ENABLE                  0x00000002
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