/[gxemul]/trunk/src/include/mpc10xreg.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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trunk/src/include/cpc700reg.h revision 20 by dpavlin, Mon Oct 8 16:19:23 2007 UTC trunk/src/include/mpc40xreg.h revision 52 by dpavlin, Thu Oct 11 12:41:35 2007 UTC
# Line 1  Line 1 
1  /*  GXemul: $Id: cpc700reg.h,v 1.2 2005/11/23 23:31:37 debug Exp $  */  /*  GXemul: $Id: cpc700reg.h,v 1.2 2005/11/23 23:31:37 debug Exp $  */
2  /*      $NetBSD: cpc700reg.h,v 1.3 2003/11/07 17:03:42 augustss Exp $   */  /*      $NetBSD: cpc700reg.h,v 1.3 2003/11/07 17:03:42 augustss Exp $   */
3    
4  #ifndef CPC700REG_H  #ifndef MPC40XREG_H
5  #define CPC700REG_H  #define MPC40XREG_H
6    
7  /*  /*
8   * Copyright (c) 2002 The NetBSD Foundation, Inc.   * Copyright (c) 2002 The NetBSD Foundation, Inc.
# Line 41  Line 41 
41   */   */
42    
43  /* PCI memory space */  /* PCI memory space */
44  #define CPC_PCI_MEM_BASE        0x80000000  #define MPC_PCI_MEM_BASE        0x80000000
45  #define CPC_PCI_MEM_END         0xf7ffffff  #define MPC_PCI_MEM_END         0xf7ffffff
46    
47  /* PCI IO space */  /* PCI IO space */
48  #define CPC_PCI_IO_BASE         0xf8000000  #define MPC_PCI_IO_BASE         0xfec00000
49  #define CPC_PCI_IO_START        0xf8800000 /* for allocation */  #if 0
50  #define CPC_PCI_IO_END          0xfbffffff  #define MPC_PCI_IO_START        0xf8800000 /* for allocation */
51    #define MPC_PCI_IO_END          0xfeffffff
52    #endif
53    
54  /* PCI config space */  /* PCI config space */
55  #define CPC_PCICFGADR           0xfec00000  #define MPC10X_MAPB_CNFG_DATA   0xfee00000
 #define   CPC_PCI_CONFIG_ENABLE         0x80000000  
 #define CPC_PCICFGDATA          0xfec00004  
56    
57    #if 0
58  /* Config space regs */  /* Config space regs */
59  #define CPC_PCI_BRDGERR         0x48  #define MPC_PCI_BRDGERR         0x48
60  #define CPC_PCI_CLEARERR        0x0000ff00  #define MPC_PCI_CLEARERR        0x0000ff00
61    
62  #define CPC_BRIDGE_OPTIONS2     0x60  #define MPC_BRIDGE_OPTIONS2     0x60
63  #define  CPC_BRIDGE_O2_ILAT_MASK        0x00f8  #define  MPC_BRIDGE_O2_ILAT_MASK        0x00f8
64  #define  CPC_BRIDGE_O2_ILAT_SHIFT       3  #define  MPC_BRIDGE_O2_ILAT_SHIFT       3
65  #define  CPC_BRIDGE_O2_ILAT_PRIM_ASYNC  18  #define  MPC_BRIDGE_O2_ILAT_PRIM_ASYNC  18
66  #define  CPC_BRIDGE_O2_SLAT_MASK        0x0f00  #define  MPC_BRIDGE_O2_SLAT_MASK        0x0f00
67  #define  CPC_BRIDGE_O2_SLAT_SHIFT       8  #define  MPC_BRIDGE_O2_SLAT_SHIFT       8
68  #define  CPC_BRIDGE_O2_2LAT_PRIM_ASYNC  2  #define  MPC_BRIDGE_O2_2LAT_PRIM_ASYNC  2
69    
70  /* PCI interrupt acknowledge & special cycle */  /* PCI interrupt acknowledge & special cycle */
71  #define CPC_INTR_ACK            0xfed00000  #define MPC_INTR_ACK            0xfed00000
72    
73  #define CPC_PMM0_LOCAL          0xff400000  #define MPC_PMM0_LOCAL          0xff400000
74  #define CPC_PMM0_MASK_ATTR      0xff400004  #define MPC_PMM0_MASK_ATTR      0xff400004
75  #define CPC_PMM0_PCI_LOW        0xff400008  #define MPC_PMM0_PCI_LOW        0xff400008
76  #define CPC_PMM0_PCI_HIGH       0xff40000c  #define MPC_PMM0_PCI_HIGH       0xff40000c
77  #define CPC_PMM1_LOCAL          0xff400010  #define MPC_PMM1_LOCAL          0xff400010
78  #define CPC_PMM1_MASK_ATTR      0xff400014  #define MPC_PMM1_MASK_ATTR      0xff400014
79  #define CPC_PMM1_PCI_LOW        0xff400018  #define MPC_PMM1_PCI_LOW        0xff400018
80  #define CPC_PMM1_PCI_HIGH       0xff40001c  #define MPC_PMM1_PCI_HIGH       0xff40001c
81  #define CPC_PMM2_LOCAL          0xff400020  #define MPC_PMM2_LOCAL          0xff400020
82  #define CPC_PMM2_MASK_ATTR      0xff400024  #define MPC_PMM2_MASK_ATTR      0xff400024
83  #define CPC_PMM2_PCI_LOW        0xff400028  #define MPC_PMM2_PCI_LOW        0xff400028
84  #define CPC_PMM2_PCI_HIGH       0xff40002c  #define MPC_PMM2_PCI_HIGH       0xff40002c
85  #define CPC_PTM1_LOCAL          0xff400030  #define MPC_PTM1_LOCAL          0xff400030
86  #define CPC_PTM1_MEMSIZE        0xff400034  #define MPC_PTM1_MEMSIZE        0xff400034
87  #define CPC_PTM2_LOCAL          0xff400038  #define MPC_PTM2_LOCAL          0xff400038
88  #define CPC_PTM2_MEMSIZE        0xff40003c  #define MPC_PTM2_MEMSIZE        0xff40003c
89    #endif
90    
91  /* serial ports */  /* serial ports */
92  #define CPC_COM0                0xff600300ULL  #define MPC_COM0                0xfc004500ULL
93  #define CPC_COM1                0xff600400ULL  #define MPC_COM1                0xfc004600ULL
94  #define CPC_COM_SPEED(bus)      ((bus) / (2 * 4))  #define MPC_COM_SPEED(bus)      ((bus) / (2 * 4))
95    
96    #if 0
97  /* processor interface registers */  /* processor interface registers */
98  #define CPC_PIF_CFGADR          0xff500000  #define MPC_PIF_CFGADR          0xff500000
99  #define  CPC_PIF_CFG_PRIFOPT1           0x00  #define  MPC_PIF_CFG_PRIFOPT1           0x00
100  #define  CPC_PIF_CFG_ERRDET1            0x04  #define  MPC_PIF_CFG_ERRDET1            0x04
101  #define  CPC_PIF_CFG_ERREN1             0x08  #define  MPC_PIF_CFG_ERREN1             0x08
102  #define  CPC_PIF_CFG_CPUERAD            0x0c  #define  MPC_PIF_CFG_CPUERAD            0x0c
103  #define  CPC_PIF_CFG_CPUERAT            0x10  #define  MPC_PIF_CFG_CPUERAT            0x10
104  #define  CPC_PIF_CFG_PLBMIFOPT          0x18  #define  MPC_PIF_CFG_PLBMIFOPT          0x18
105  #define  CPC_PIF_CFG_PLBMTLSA1          0x20  #define  MPC_PIF_CFG_PLBMTLSA1          0x20
106  #define  CPC_PIF_CFG_PLBMTLEA1          0x24  #define  MPC_PIF_CFG_PLBMTLEA1          0x24
107  #define  CPC_PIF_CFG_PLBMTLSA2          0x28  #define  MPC_PIF_CFG_PLBMTLSA2          0x28
108  #define  CPC_PIF_CFG_PLBMTLEA2          0x2c  #define  MPC_PIF_CFG_PLBMTLEA2          0x2c
109  #define  CPC_PIF_CFG_PLBMTLSA3          0x30  #define  MPC_PIF_CFG_PLBMTLSA3          0x30
110  #define  CPC_PIF_CFG_PLBMTLEA3          0x34  #define  MPC_PIF_CFG_PLBMTLEA3          0x34
111  #define  CPC_PIF_CFG_PLBSNSSA0          0x38  #define  MPC_PIF_CFG_PLBSNSSA0          0x38
112  #define  CPC_PIF_CFG_PLBSNSEA0          0x3c  #define  MPC_PIF_CFG_PLBSNSEA0          0x3c
113  #define  CPC_PIF_CFG_BESR               0x40  #define  MPC_PIF_CFG_BESR               0x40
114  #define  CPC_PIF_CFG_BESRSET            0x44  #define  MPC_PIF_CFG_BESRSET            0x44
115  #define  CPC_PIF_CFG_BEAR               0x4c  #define  MPC_PIF_CFG_BEAR               0x4c
116  #define  CPC_PIF_CFG_PLBSWRINT          0x80  #define  MPC_PIF_CFG_PLBSWRINT          0x80
117  #define CPC_PIF_CFGDATA         0xff500004  #define MPC_PIF_CFGDATA         0xff500004
118    #endif
119    
120  /* interrupt controller */  /* interrupt controller */
121  #define CPC_UIC_BASE            0xff500880  #define MPC_UIC_BASE            0xfec00000
122  #define CPC_UIC_SIZE            0x00000024  #define MPC_UIC_SIZE            0x00000024
123  #define CPC_UIC_SR              0x00000000 /* UIC status (read/clear) */  #define MPC_UIC_SR              0x00000000 /* UIC status (read/clear) */
124  #define CPC_UIC_SRS             0x00000004 /* UIC status (set) */  #define MPC_UIC_SRS             0x00000004 /* UIC status (set) */
125  #define CPC_UIC_ER              0x00000008 /* UIC enable */  #define MPC_UIC_ER              0x00000008 /* UIC enable */
126  #define CPC_UIC_CR              0x0000000c /* UIC critical */  #define MPC_UIC_CR              0x0000000c /* UIC critical */
127  #define CPC_UIC_PR              0x00000010 /* UIC polarity 0=low, 1=high*/  #define MPC_UIC_PR              0x00000010 /* UIC polarity 0=low, 1=high*/
128  #define CPC_UIC_TR              0x00000014 /* UIC trigger 0=level; 1=edge */  #define MPC_UIC_TR              0x00000014 /* UIC trigger 0=level; 1=edge */
129  #define CPC_UIC_MSR             0x00000018 /* UIC masked status */  #define MPC_UIC_MSR             0x00000018 /* UIC masked status */
130  #define CPC_UIC_VR              0x0000001c /* UIC vector */  #define MPC_UIC_VR              0x0000001c /* UIC vector */
131  #define CPC_UIC_VCR             0x00000020 /* UIC vector configuration */  #define MPC_UIC_VCR             0x00000020 /* UIC vector configuration */
132  #define   CPC_UIC_CVR_PRI         0x00000001 /* 0=intr31 high, 1=intr0 high */  #define   MPC_UIC_CVR_PRI         0x00000001 /* 0=intr31 high, 1=intr0 high */
133  /*  /*
134   * if intr0 high then interrupt vector at (vcr&~3) + N*512   * if intr0 high then interrupt vector at (vcr&~3) + N*512
135   * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512   * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512
# Line 133  Line 137 
137    
138  /* UIC interrupt bits.  Note, MSB is bit 0 */  /* UIC interrupt bits.  Note, MSB is bit 0 */
139  /* Internal */  /* Internal */
140  #define CPC_IB_ECC              0  #define MPC_IB_ECC              0
141  #define CPC_IB_PCI_WR_RANGE     1  #define MPC_IB_PCI_WR_RANGE     1
142  #define CPC_IB_PCI_WR_CMD       2  #define MPC_IB_PCI_WR_CMD       2
143  #define CPC_IB_UART_0           3  #define MPC_IB_UART_0           3
144  #define CPC_IB_UART_1           4  #define MPC_IB_UART_1           4
145  #define CPC_IB_IIC_0            5  #define MPC_IB_IIC_0            5
146  #define CPC_IB_IIC_1            6  #define MPC_IB_IIC_1            6
147  /* 6-16 GPT compare&capture */  /* 6-16 GPT compare&capture */
148  /* 20-31 external */  /* 20-31 external */
149  #define CPC_IB_EXT0             20  #define MPC_IB_EXT0             20
150  #define CPC_IB_EXT1             21  #define MPC_IB_EXT1             21
151  #define CPC_IB_EXT2             22  #define MPC_IB_EXT2             22
152  #define CPC_IB_EXT3             23  #define MPC_IB_EXT3             23
153  #define CPC_IB_EXT4             24  #define MPC_IB_EXT4             24
154  #define CPC_IB_EXT5             25  #define MPC_IB_EXT5             25
155  #define CPC_IB_EXT6             26  #define MPC_IB_EXT6             26
156  #define CPC_IB_EXT7             27  #define MPC_IB_EXT7             27
157  #define CPC_IB_EXT8             28  #define MPC_IB_EXT8             28
158  #define CPC_IB_EXT9             29  #define MPC_IB_EXT9             29
159  #define CPC_IB_EXT10            30  #define MPC_IB_EXT10            30
160  #define CPC_IB_EXT11            31  #define MPC_IB_EXT11            31
   
 #define CPC_INTR_MASK(irq) (0x80000000 >> (irq))  
161    
162    #define MPC_INTR_MASK(irq) (0x80000000 >> (irq))
163    
164    #if 0
165  /* IIC */  /* IIC */
166  #define CPC_IIC0                0xff620000  #define MPC_IIC0                0xfc020000
167  #define CPC_IIC1                0xff630000  #define MPC_IIC1                0xfc030000
168  #define CPC_IIC_SIZE            0x00000014  #define MPC_IIC_SIZE            0x00000014
169  /* offsets from base */  /* offsets from base */
170  #define CPC_IIC_MDBUF           0x00000000  #define MPC_IIC_MDBUF           0x00000000
171  #define CPC_IIC_SDBUF           0x00000002  #define MPC_IIC_SDBUF           0x00000002
172  #define CPC_IIC_LMADR           0x00000004  #define MPC_IIC_LMADR           0x00000004
173  #define CPC_IIC_HNADR           0x00000005  #define MPC_IIC_HNADR           0x00000005
174  #define CPC_IIC_CNTL            0x00000006  #define MPC_IIC_CNTL            0x00000006
175  #define CPC_IIC_MDCNTL          0x00000007  #define MPC_IIC_MDCNTL          0x00000007
176  #define CPC_IIC_STS             0x00000008  #define MPC_IIC_STS             0x00000008
177  #define CPC_IIC_EXTSTS          0x00000009  #define MPC_IIC_EXTSTS          0x00000009
178  #define CPC_IIC_LSADR           0x0000000a  #define MPC_IIC_LSADR           0x0000000a
179  #define CPC_IIC_HSADR           0x0000000b  #define MPC_IIC_HSADR           0x0000000b
180  #define CPC_IIC_CLKDIV          0x0000000c  #define MPC_IIC_CLKDIV          0x0000000c
181  #define CPC_IIC_INTRMSK         0x0000000d  #define MPC_IIC_INTRMSK         0x0000000d
182  #define CPC_IIC_FRCNT           0x0000000e  #define MPC_IIC_FRCNT           0x0000000e
183  #define CPC_IIC_TCNTLSS         0x0000000f  #define MPC_IIC_TCNTLSS         0x0000000f
184  #define CPC_IIC_DIRECTCNTL      0x00000010  #define MPC_IIC_DIRECTCNTL      0x00000010
185    
186  /* timer */  /* timer */
187  #define CPC_TIMER               0xff650000  #define MPC_TIMER               0xfc050000
188  #define CPC_GPTTBC              0x00000000  #define MPC_GPTTBC              0x00000000
189    
190    #endif
191    
192  #endif  /*  CPC700REG_H  */  #endif  /*  MPC40XREG_H  */
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