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/* GXemul: $Id: cpc700reg.h,v 1.2 2005/11/23 23:31:37 debug Exp $ */ |
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/* $NetBSD: cpc700reg.h,v 1.3 2003/11/07 17:03:42 augustss Exp $ */ |
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#ifndef MPC40XREG_H |
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#define MPC40XREG_H |
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/* |
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* Copyright (c) 2002 The NetBSD Foundation, Inc. |
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* All rights reserved. |
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* |
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* This code is derived from software contributed to The NetBSD Foundation |
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* by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. All advertising materials mentioning features or use of this software |
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* must display the following acknowledgement: |
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* This product includes software developed by the NetBSD |
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* Foundation, Inc. and its contributors. |
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* 4. Neither the name of The NetBSD Foundation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/* PCI memory space */ |
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#define MPC_PCI_MEM_BASE 0x80000000 |
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#define MPC_PCI_MEM_END 0xf7ffffff |
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/* PCI IO space */ |
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#define MPC_PCI_IO_BASE 0xfec00000 |
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#define MPC_PCI_IO_START 0xf8800000 /* for allocation */ |
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#define MPC_PCI_IO_END 0xfeffffff |
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/* PCI config space */ |
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#define MPC_PCICFGADR 0xfee00000 |
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#define MPC_PCI_CONFIG_ENABLE 0x80000000 |
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#define MPC_PCICFGDATA 0xfee00004 |
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/* Config space regs */ |
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#define MPC_PCI_BRDGERR 0x48 |
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#define MPC_PCI_CLEARERR 0x0000ff00 |
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#define MPC_BRIDGE_OPTIONS2 0x60 |
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#define MPC_BRIDGE_O2_ILAT_MASK 0x00f8 |
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#define MPC_BRIDGE_O2_ILAT_SHIFT 3 |
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#define MPC_BRIDGE_O2_ILAT_PRIM_ASYNC 18 |
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#define MPC_BRIDGE_O2_SLAT_MASK 0x0f00 |
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#define MPC_BRIDGE_O2_SLAT_SHIFT 8 |
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#define MPC_BRIDGE_O2_2LAT_PRIM_ASYNC 2 |
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/* PCI interrupt acknowledge & special cycle */ |
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#define MPC_INTR_ACK 0xfed00000 |
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#define MPC_PMM0_LOCAL 0xff400000 |
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#define MPC_PMM0_MASK_ATTR 0xff400004 |
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#define MPC_PMM0_PCI_LOW 0xff400008 |
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#define MPC_PMM0_PCI_HIGH 0xff40000c |
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#define MPC_PMM1_LOCAL 0xff400010 |
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#define MPC_PMM1_MASK_ATTR 0xff400014 |
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#define MPC_PMM1_PCI_LOW 0xff400018 |
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#define MPC_PMM1_PCI_HIGH 0xff40001c |
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#define MPC_PMM2_LOCAL 0xff400020 |
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#define MPC_PMM2_MASK_ATTR 0xff400024 |
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#define MPC_PMM2_PCI_LOW 0xff400028 |
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#define MPC_PMM2_PCI_HIGH 0xff40002c |
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#define MPC_PTM1_LOCAL 0xff400030 |
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#define MPC_PTM1_MEMSIZE 0xff400034 |
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#define MPC_PTM2_LOCAL 0xff400038 |
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#define MPC_PTM2_MEMSIZE 0xff40003c |
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/* serial ports */ |
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#define MPC_COM0 0xfc004500ULL |
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#define MPC_COM1 0xfc004600ULL |
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#define MPC_COM_SPEED(bus) ((bus) / (2 * 4)) |
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/* processor interface registers */ |
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#define MPC_PIF_CFGADR 0xff500000 |
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#define MPC_PIF_CFG_PRIFOPT1 0x00 |
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#define MPC_PIF_CFG_ERRDET1 0x04 |
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#define MPC_PIF_CFG_ERREN1 0x08 |
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#define MPC_PIF_CFG_CPUERAD 0x0c |
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#define MPC_PIF_CFG_CPUERAT 0x10 |
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#define MPC_PIF_CFG_PLBMIFOPT 0x18 |
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#define MPC_PIF_CFG_PLBMTLSA1 0x20 |
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#define MPC_PIF_CFG_PLBMTLEA1 0x24 |
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#define MPC_PIF_CFG_PLBMTLSA2 0x28 |
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#define MPC_PIF_CFG_PLBMTLEA2 0x2c |
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#define MPC_PIF_CFG_PLBMTLSA3 0x30 |
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#define MPC_PIF_CFG_PLBMTLEA3 0x34 |
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#define MPC_PIF_CFG_PLBSNSSA0 0x38 |
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#define MPC_PIF_CFG_PLBSNSEA0 0x3c |
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#define MPC_PIF_CFG_BESR 0x40 |
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#define MPC_PIF_CFG_BESRSET 0x44 |
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#define MPC_PIF_CFG_BEAR 0x4c |
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#define MPC_PIF_CFG_PLBSWRINT 0x80 |
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#define MPC_PIF_CFGDATA 0xff500004 |
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/* interrupt controller */ |
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#define MPC_UIC_BASE 0xff500880 |
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#define MPC_UIC_SIZE 0x00000024 |
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#define MPC_UIC_SR 0x00000000 /* UIC status (read/clear) */ |
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#define MPC_UIC_SRS 0x00000004 /* UIC status (set) */ |
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#define MPC_UIC_ER 0x00000008 /* UIC enable */ |
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#define MPC_UIC_CR 0x0000000c /* UIC critical */ |
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#define MPC_UIC_PR 0x00000010 /* UIC polarity 0=low, 1=high*/ |
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#define MPC_UIC_TR 0x00000014 /* UIC trigger 0=level; 1=edge */ |
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#define MPC_UIC_MSR 0x00000018 /* UIC masked status */ |
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#define MPC_UIC_VR 0x0000001c /* UIC vector */ |
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#define MPC_UIC_VCR 0x00000020 /* UIC vector configuration */ |
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#define MPC_UIC_CVR_PRI 0x00000001 /* 0=intr31 high, 1=intr0 high */ |
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/* |
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* if intr0 high then interrupt vector at (vcr&~3) + N*512 |
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* if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512 |
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*/ |
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/* UIC interrupt bits. Note, MSB is bit 0 */ |
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/* Internal */ |
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#define MPC_IB_ECC 0 |
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#define MPC_IB_PCI_WR_RANGE 1 |
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#define MPC_IB_PCI_WR_CMD 2 |
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#define MPC_IB_UART_0 3 |
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#define MPC_IB_UART_1 4 |
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#define MPC_IB_IIC_0 5 |
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#define MPC_IB_IIC_1 6 |
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/* 6-16 GPT compare&capture */ |
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/* 20-31 external */ |
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#define MPC_IB_EXT0 20 |
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#define MPC_IB_EXT1 21 |
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#define MPC_IB_EXT2 22 |
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#define MPC_IB_EXT3 23 |
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#define MPC_IB_EXT4 24 |
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#define MPC_IB_EXT5 25 |
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#define MPC_IB_EXT6 26 |
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#define MPC_IB_EXT7 27 |
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#define MPC_IB_EXT8 28 |
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#define MPC_IB_EXT9 29 |
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#define MPC_IB_EXT10 30 |
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#define MPC_IB_EXT11 31 |
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#define MPC_INTR_MASK(irq) (0x80000000 >> (irq)) |
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#if 0 |
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/* IIC */ |
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#define MPC_IIC0 0xfc020000 |
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#define MPC_IIC1 0xfc030000 |
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#define MPC_IIC_SIZE 0x00000014 |
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/* offsets from base */ |
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#define MPC_IIC_MDBUF 0x00000000 |
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#define MPC_IIC_SDBUF 0x00000002 |
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#define MPC_IIC_LMADR 0x00000004 |
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#define MPC_IIC_HNADR 0x00000005 |
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#define MPC_IIC_CNTL 0x00000006 |
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#define MPC_IIC_MDCNTL 0x00000007 |
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#define MPC_IIC_STS 0x00000008 |
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#define MPC_IIC_EXTSTS 0x00000009 |
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#define MPC_IIC_LSADR 0x0000000a |
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#define MPC_IIC_HSADR 0x0000000b |
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#define MPC_IIC_CLKDIV 0x0000000c |
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#define MPC_IIC_INTRMSK 0x0000000d |
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#define MPC_IIC_FRCNT 0x0000000e |
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#define MPC_IIC_TCNTLSS 0x0000000f |
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#define MPC_IIC_DIRECTCNTL 0x00000010 |
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/* timer */ |
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#define MPC_TIMER 0xfc050000 |
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#define MPC_GPTTBC 0x00000000 |
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#endif |
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#endif /* MPC40XREG_H */ |
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