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#define MIPS_CPU_TYPES_H |
#define MIPS_CPU_TYPES_H |
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/* |
/* |
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* Copyright (C) 2003-2006 Anders Gavare. All rights reserved. |
* Copyright (C) 2003-2007 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: mips_cpu_types.h,v 1.17 2006/05/21 11:15:25 debug Exp $ |
* $Id: mips_cpu_types.h,v 1.19 2007/02/10 13:31:20 debug Exp $ |
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* |
* |
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* MIPS CPU types. |
* MIPS CPU types. |
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*/ |
*/ |
101 |
{ "RM9000", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* This is totally bogus */ \ |
{ "RM9000", 0x34 /*?*/, 0x0 /* ? */,DCOUNT,EXC4K, MMU4K, 4, 0, 48, 4,14,5,1,14,5,1,18, 6, 1 }, /* This is totally bogus */ \ |
102 |
{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 1, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
{ "RC32334", MIPS_RC32300,0x00, 0, EXC32, MMU4K, 32, 1, 16, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \ |
103 |
{ "4Kc", 0x100+MIPS_4Kc, 1, 0, EXC32, MMU32, 32, 1, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
{ "4Kc", 0x100+MIPS_4Kc, 1, 0, EXC32, MMU32, 32, 1, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
104 |
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{ "4KEc", 0x100+MIPS_4KEc_R2, 1, 0, EXC32, MMU32, 32, 2, 16, 4,14,4,2,14,4,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
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{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 1, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
{ "5Kc", 0x100+MIPS_5Kc, 1, 0, EXC64, MMU64, 64, 1, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
106 |
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{ "5KE", 0x100+MIPS_5KE, 1, 0, EXC64, MMU64, 64, 2, 48, 4,15,5,2,15,5,2, 0, 0, 0 }, /* DCOUNT? instrs/cycle? BOGUS, TODO */ \ |
107 |
{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "BCM4710", 0x000240, 0x00, 0, EXC32, MMU32, 32, 1, 32, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
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{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 1, 32, 2,13,4,1,12,4,1, 0, 0, 0 }, /* 2ways I, 2ways D */ \ |
{ "BCM4712", 0x000290, 0x07, 0, EXC32, MMU32, 32, 1, 32, 2,13,4,1,12,4,1, 0, 0, 0 }, /* 2ways I, 2ways D */ \ |
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{ "AU1000", 0x00302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |
{ "AU1000", 0x00302, 0x01, 0, EXC32, MMU32, 32, 1, 32, 2,14,5,2,14,5,2, 0, 0, 0 }, /* TODO: this is just bogus */ \ |