28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu_x86.h,v 1.7 2005/04/20 02:05:57 debug Exp $ |
* $Id: cpu_x86.h,v 1.31 2005/05/29 19:21:05 debug Exp $ |
32 |
*/ |
*/ |
33 |
|
|
34 |
#include "misc.h" |
#include "misc.h" |
41 |
#define x86_reg_names { \ |
#define x86_reg_names { \ |
42 |
"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ |
"ax", "cx", "dx", "bx", "sp", "bp", "si", "di", \ |
43 |
"08", "09", "10", "11", "12", "13", "14", "15" } |
"08", "09", "10", "11", "12", "13", "14", "15" } |
44 |
|
#define x86_reg_names_bytes { \ |
45 |
|
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh" } |
46 |
|
|
47 |
#define X86_R_AX 0 |
#define X86_R_AX 0 |
48 |
#define X86_R_CX 1 |
#define X86_R_CX 1 |
63 |
#define X86_S_FS 4 |
#define X86_S_FS 4 |
64 |
#define X86_S_GS 5 |
#define X86_S_GS 5 |
65 |
|
|
66 |
#define x86_seg_names { "es", "cs", "ss", "ds", "es", "gs", "xx6", "xx7" } |
#define x86_seg_names { "es", "cs", "ss", "ds", "fs", "gs", "segr6", "segr7" } |
67 |
|
|
68 |
#define N_X86_CREGS 8 |
#define N_X86_CREGS 8 |
69 |
|
|
70 |
|
#define N_X86_DREGS 8 |
71 |
|
|
72 |
#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } |
#define x86_cond_names { "o", "b", "z", "be", "s", "p", "l", "le" } |
73 |
#define N_X86_CONDS 8 |
#define N_X86_CONDS 8 |
74 |
|
|
75 |
#define X86_MODEL_8086 1 |
#define X86_MODEL_8086 1 |
76 |
#define X86_MODEL_80386 2 |
#define X86_MODEL_80286 2 |
77 |
#define X86_MODEL_PENTIUM 3 |
#define X86_MODEL_80386 3 |
78 |
#define X86_MODEL_AMD64 4 |
#define X86_MODEL_80486 4 |
79 |
|
#define X86_MODEL_PENTIUM 5 |
80 |
|
#define X86_MODEL_AMD64 6 |
81 |
|
|
82 |
struct x86_model { |
struct x86_model { |
83 |
int model_number; |
int model_number; |
86 |
|
|
87 |
#define x86_models { \ |
#define x86_models { \ |
88 |
{ X86_MODEL_8086, "8086" }, \ |
{ X86_MODEL_8086, "8086" }, \ |
89 |
|
{ X86_MODEL_80286, "80286" }, \ |
90 |
{ X86_MODEL_80386, "80386" }, \ |
{ X86_MODEL_80386, "80386" }, \ |
91 |
|
{ X86_MODEL_80486, "80486" }, \ |
92 |
{ X86_MODEL_PENTIUM, "PENTIUM" }, \ |
{ X86_MODEL_PENTIUM, "PENTIUM" }, \ |
93 |
{ X86_MODEL_AMD64, "AMD64" }, \ |
{ X86_MODEL_AMD64, "AMD64" }, \ |
94 |
{ 0, NULL } \ |
{ 0, NULL } \ |
95 |
} |
} |
96 |
|
|
97 |
|
|
98 |
|
struct descriptor_cache { |
99 |
|
int valid; |
100 |
|
int default_op_size; |
101 |
|
int access_rights; |
102 |
|
int descr_type; |
103 |
|
int readable; |
104 |
|
int writable; |
105 |
|
int granularity; |
106 |
|
uint64_t base; |
107 |
|
uint64_t limit; |
108 |
|
}; |
109 |
|
|
110 |
|
|
111 |
struct x86_cpu { |
struct x86_cpu { |
112 |
struct x86_model model; |
struct x86_model model; |
113 |
|
|
114 |
int bits; /* 16, 32, or 64 */ |
int halted; |
115 |
int mode; /* 16, 32, or 64 */ |
int interrupt_asserted; |
116 |
|
|
117 |
|
int cursegment; /* NOTE: 0..N_X86_SEGS-1 */ |
118 |
|
int seg_override; /* 0 or 1 */ |
119 |
|
|
120 |
|
uint64_t tsc; /* time stamp counter */ |
121 |
|
|
122 |
uint16_t cursegment; /* for 16-bit memory_rw */ |
uint64_t gdtr; /* global descriptor table */ |
123 |
|
uint32_t gdtr_limit; |
124 |
|
uint64_t idtr; /* interrupt descriptor table */ |
125 |
|
uint32_t idtr_limit; |
126 |
|
|
127 |
|
uint16_t tr; /* task register */ |
128 |
|
uint64_t tr_base; |
129 |
|
uint32_t tr_limit; |
130 |
|
uint16_t ldtr; /* local descriptor table register */ |
131 |
|
uint64_t ldtr_base; |
132 |
|
uint32_t ldtr_limit; |
133 |
|
|
134 |
uint64_t rflags; |
uint64_t rflags; |
135 |
uint64_t cr[N_X86_CREGS]; |
uint64_t cr[N_X86_CREGS]; /* control registers */ |
136 |
|
uint64_t dr[N_X86_DREGS]; /* debug registers */ |
137 |
|
|
138 |
uint16_t s[N_X86_SEGS]; |
uint16_t s[N_X86_SEGS]; /* segment selectors */ |
139 |
uint64_t r[N_X86_REGS]; |
struct descriptor_cache descr_cache[N_X86_SEGS]; |
140 |
|
|
141 |
|
uint64_t r[N_X86_REGS]; /* GPRs */ |
142 |
|
|
143 |
|
/* FPU: */ |
144 |
|
uint16_t fpu_sw; /* status word */ |
145 |
|
uint16_t fpu_cw; /* control word */ |
146 |
|
|
147 |
|
/* MSRs: */ |
148 |
|
uint64_t efer; |
149 |
}; |
}; |
150 |
|
|
151 |
|
|
162 |
#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ |
#define X86_FLAGS_NT (1<<14) /* Nested Task Flag */ |
163 |
#define X86_FLAGS_RF (1<<16) /* Resume Flag */ |
#define X86_FLAGS_RF (1<<16) /* Resume Flag */ |
164 |
#define X86_FLAGS_VM (1<<17) /* VM86 Flag */ |
#define X86_FLAGS_VM (1<<17) /* VM86 Flag */ |
165 |
|
#define X86_FLAGS_AC (1<<18) /* Alignment Check */ |
166 |
|
#define X86_FLAGS_VIF (1<<19) /* ? */ |
167 |
|
#define X86_FLAGS_VIP (1<<20) /* ? */ |
168 |
|
#define X86_FLAGS_ID (1<<21) /* CPUID present */ |
169 |
|
|
170 |
|
#define X86_CR0_PE 0x00000001 /* Protection Enable */ |
171 |
|
#define X86_CR0_MP 0x00000002 |
172 |
|
#define X86_CR0_EM 0x00000004 |
173 |
|
#define X86_CR0_TS 0x00000008 |
174 |
|
#define X86_CR0_ET 0x00000010 |
175 |
|
#define X86_CR0_NE 0x00000020 |
176 |
|
#define X86_CR0_WP 0x00010000 |
177 |
|
#define X86_CR0_AM 0x00040000 |
178 |
|
#define X86_CR0_NW 0x20000000 |
179 |
|
#define X86_CR0_CD 0x40000000 |
180 |
|
#define X86_CR0_PG 0x80000000 /* Paging Enable */ |
181 |
|
|
182 |
|
#define X86_CR4_OSXMEX 0x00000400 |
183 |
|
#define X86_CR4_OSFXSR 0x00000200 |
184 |
|
#define X86_CR4_PCE 0x00000100 |
185 |
|
#define X86_CR4_PGE 0x00000080 |
186 |
|
#define X86_CR4_MCE 0x00000040 |
187 |
|
#define X86_CR4_PAE 0x00000020 |
188 |
|
#define X86_CR4_PSE 0x00000010 |
189 |
|
#define X86_CR4_DE 0x00000008 |
190 |
|
#define X86_CR4_TSD 0x00000004 /* Time Stamp Disable */ |
191 |
|
#define X86_CR4_PVI 0x00000002 |
192 |
|
#define X86_CR4_VME 0x00000001 |
193 |
|
|
194 |
|
/* EFER bits: */ |
195 |
|
#define X86_EFER_FFXSR 0x00004000 |
196 |
|
#define X86_EFER_LMSLE 0x00002000 |
197 |
|
#define X86_EFER_NXE 0x00000800 |
198 |
|
#define X86_EFER_LMA 0x00000400 |
199 |
|
#define X86_EFER_LME 0x00000100 /* Long Mode (64-bit) */ |
200 |
|
#define X86_EFER_SCE 0x00000001 |
201 |
|
|
202 |
|
/* CPUID feature bits: */ |
203 |
|
#define X86_CPUID_ECX_ETPRD 0x00004000 |
204 |
|
#define X86_CPUID_ECX_CX16 0x00002000 /* cmpxchg16b */ |
205 |
|
#define X86_CPUID_ECX_CID 0x00000400 |
206 |
|
#define X86_CPUID_ECX_TM2 0x00000100 |
207 |
|
#define X86_CPUID_ECX_EST 0x00000080 |
208 |
|
#define X86_CPUID_ECX_DSCPL 0x00000010 |
209 |
|
#define X86_CPUID_ECX_MON 0x00000004 |
210 |
|
#define X86_CPUID_ECX_SSE3 0x00000001 |
211 |
|
#define X86_CPUID_EDX_PBE 0x80000000 /* pending break event */ |
212 |
|
#define X86_CPUID_EDX_IA64 0x40000000 |
213 |
|
#define X86_CPUID_EDX_TM1 0x20000000 /* thermal interrupt */ |
214 |
|
#define X86_CPUID_EDX_HTT 0x10000000 /* hyper threading */ |
215 |
|
#define X86_CPUID_EDX_SS 0x08000000 /* self-snoop */ |
216 |
|
#define X86_CPUID_EDX_SSE2 0x04000000 |
217 |
|
#define X86_CPUID_EDX_SSE 0x02000000 |
218 |
|
#define X86_CPUID_EDX_FXSR 0x01000000 |
219 |
|
#define X86_CPUID_EDX_MMX 0x00800000 |
220 |
|
#define X86_CPUID_EDX_ACPI 0x00400000 |
221 |
|
#define X86_CPUID_EDX_DTES 0x00200000 |
222 |
|
#define X86_CPUID_EDX_CLFL 0x00080000 |
223 |
|
#define X86_CPUID_EDX_PSN 0x00040000 |
224 |
|
#define X86_CPUID_EDX_PSE36 0x00020000 |
225 |
|
#define X86_CPUID_EDX_PAT 0x00010000 |
226 |
|
#define X86_CPUID_EDX_CMOV 0x00008000 |
227 |
|
#define X86_CPUID_EDX_MCA 0x00004000 |
228 |
|
#define X86_CPUID_EDX_PGE 0x00002000 /* global bit in PDE/PTE */ |
229 |
|
#define X86_CPUID_EDX_MTRR 0x00001000 |
230 |
|
#define X86_CPUID_EDX_SEP 0x00000800 /* sysenter/sysexit */ |
231 |
|
#define X86_CPUID_EDX_APIC 0x00000200 |
232 |
|
#define X86_CPUID_EDX_CX8 0x00000100 /* cmpxchg8b */ |
233 |
|
#define X86_CPUID_EDX_MCE 0x00000080 |
234 |
|
#define X86_CPUID_EDX_PAE 0x00000040 |
235 |
|
#define X86_CPUID_EDX_MSR 0x00000020 |
236 |
|
#define X86_CPUID_EDX_TSC 0x00000010 |
237 |
|
#define X86_CPUID_EDX_PSE 0x00000008 |
238 |
|
#define X86_CPUID_EDX_DE 0x00000004 |
239 |
|
#define X86_CPUID_EDX_VME 0x00000002 |
240 |
|
#define X86_CPUID_EDX_FPU 0x00000001 |
241 |
|
|
242 |
|
/* Extended CPUID flags: */ |
243 |
|
#define X86_CPUID_EXT_ECX_CR8D 0x00000010 |
244 |
|
#define X86_CPUID_EXT_ECX_CMP 0x00000002 |
245 |
|
#define X86_CPUID_EXT_ECX_AHF64 0x00000001 |
246 |
|
#define X86_CPUID_EXT_EDX_LM 0x20000000 /* AMD64 Long Mode */ |
247 |
|
#define X86_CPUID_EXT_EDX_FFXSR 0x02000000 |
248 |
|
/* TODO: Many bits are duplicated in the Extended CPUID bits! */ |
249 |
|
|
250 |
|
#define X86_IO_BASE 0x1000000000ULL |
251 |
|
|
252 |
|
/* Privilege level in the lowest 2 bits of a selector: */ |
253 |
|
#define X86_PL_MASK 0x0003 |
254 |
|
#define X86_RING0 0 |
255 |
|
#define X86_RING1 1 |
256 |
|
#define X86_RING2 2 |
257 |
|
#define X86_RING3 3 |
258 |
|
|
259 |
|
#define DESCR_TYPE_CODE 1 |
260 |
|
#define DESCR_TYPE_DATA 2 |
261 |
|
|
262 |
|
|
263 |
|
#define PROTECTED_MODE (cpu->cd.x86.cr[0] & X86_CR0_PE) |
264 |
|
#define REAL_MODE (!PROTECTED_MODE) |
265 |
|
|
266 |
/* cpu_x86.c: */ |
/* cpu_x86.c: */ |
267 |
|
void reload_segment_descriptor(struct cpu *cpu, int segnr, int selector, |
268 |
|
uint64_t *curpcp); |
269 |
|
int x86_interrupt(struct cpu *cpu, int nr, int errcode); |
270 |
int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int x86_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
271 |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
272 |
int x86_cpu_family_init(struct cpu_family *); |
int x86_cpu_family_init(struct cpu_family *); |