--- trunk/src/include/cpu_sparc.h 2007/10/08 16:19:56 24 +++ trunk/src/include/cpu_sparc.h 2007/10/08 16:21:34 36 @@ -2,7 +2,7 @@ #define CPU_SPARC_H /* - * Copyright (C) 2005-2006 Anders Gavare. All rights reserved. + * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -28,7 +28,7 @@ * SUCH DAMAGE. * * - * $Id: cpu_sparc.h,v 1.38 2006/05/18 05:10:44 debug Exp $ + * $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $ */ #include "misc.h" @@ -40,7 +40,10 @@ /* SPARC CPU types: */ struct sparc_cpu_type_def { char *name; - int bits; + int v; /* v8, v9 etc */ + int h; /* hypervisor? sun4v = 1 */ + int bits; /* 32 or 64 */ + int nwindows; /* usually 8 or more */ int icache_shift; int ilinesize; int iway; @@ -52,14 +55,22 @@ int l2way; }; +/* NOTE/TODO: Maybe some of the types listed below as v8 are in + fact v7; I haven't had time to check. Also, the nwindows value is + just bogus. */ +/* See http://www.sparc.com/standards/v8v9-numbers.html for + implementation numbers! */ +/* Note/TODO: sun4v is listed as 10 */ + #define SPARC_CPU_TYPE_DEFS { \ - { "TMS390Z50", 32, 14,5,2, 14,5,2, 0,0,0 }, \ - { "MB86904", 32, 14,5,2, 13,4,2, 0,0,0 }, \ - { "MB86907", 32, 14,5,2, 14,5,2, 19,5,1 }, \ - { "UltraSPARC", 64, 14,5,4, 14,5,4, 19,6,1 }, \ - { "UltraSPARC-IIi", 64, 15,5,2, 14,5,2, 21,6,1 }, \ - { "UltraSPARC-II", 64, 15,5,2, 14,5,2, 22,6,1 }, \ - { NULL, 0, 0,0,0, 0,0,0, 0,0,0 } \ + { "TMS390Z50", 8, 0, 32, 8, 14,5,2, 14,5,2, 0,0,0 }, \ + { "MB86904", 8, 0, 32, 8, 14,5,2, 13,4,2, 0,0,0 }, \ + { "MB86907", 8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 }, \ + { "UltraSPARC", 9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 }, \ + { "UltraSPARC-IIi", 9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 }, \ + { "UltraSPARC-II", 9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ + { "T1", 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 }, \ + { NULL, 0, 0, 0, 0, 0,0,0, 0,0,0, 0,0,0 } \ } @@ -83,6 +94,9 @@ #define N_SPARC_REG 32 +#define N_SPARC_GLOBAL_REG 8 +#define N_SPARC_INOUT_REG 8 +#define N_SPARC_LOCAL_REG 8 #define SPARC_REG_NAMES { \ "g0","g1","g2","g3","g4","g5","g6","g7", \ "o0","o1","o2","o3","o4","o5","sp","o7", \ @@ -128,11 +142,11 @@ #define SPARC_PREG_NAMES { \ "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl", \ "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin", \ - "wstate", "reserved15", "reserved16", "reserved17", "reserved18", \ + "wstate", "fq", "reserved16", "reserved17", "reserved18", \ "reserved19", "reserved20", "reserved21", "reserved22", \ "reserved23", "reserved24", "reserved25", "reserved26", \ "reserved27", "reserved28", "reserved29", "reserved30", \ - "reserved31" } + "ver" } #define N_SPARC_BRANCH_TYPES 16 #define SPARC_BRANCH_NAMES { \ @@ -158,8 +172,8 @@ #define N_LOADSTORE_TYPES 64 #define SPARC_LOADSTORE_NAMES { \ - "ld","ldub","lduh","ldd", "st","stb","sth","std", \ - "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ + "lduw","ldub","lduh","ldd", "st","stb","sth","std", \ + "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap", \ "lda","lduba","lduha","ldda", "sta","stba","stha","stda", \ "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa", \ "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf", \ @@ -168,9 +182,10 @@ "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" } -/* Max number of Trap Levels and Windows: */ -#define MAXTL 4 -#define MAXWIN 32 +/* Max number of Trap Levels, Global Levels, and Register Windows: */ +#define MAXTL 6 +#define MAXGL 7 +#define N_REG_WINDOWS 8 struct sparc_cpu { @@ -179,6 +194,11 @@ /* Registers in the Current Window: */ uint64_t r[N_SPARC_REG]; + uint64_t r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG]; + uint64_t r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG]; + + uint64_t r_global[MAXGL+1][N_SPARC_GLOBAL_REG]; + uint64_t scratch; /* Pre-SPARCv9 specific: */ @@ -205,6 +225,7 @@ uint8_t ccr; /* Condition Code Register */ uint8_t asi; /* Address Space Identifier */ uint8_t tl; /* Trap Level Register */ + uint8_t gl; /* Global Level Register */ uint8_t pil; /* Processor Interrupt Level Reg. */ uint64_t tpc[MAXTL]; /* Trap Program Counter */ @@ -214,6 +235,13 @@ uint64_t tba; /* Trap Base Address */ + uint64_t hpstate; /* Hyper-Privileged State Register */ + uint64_t htstate[MAXTL]; /* Hyper-Privileged Trap State */ + uint64_t hintp; /* Hyper-Privileged InterruptPending */ + uint64_t htba; /* Hyper-Privileged Trap Base Addr */ + uint64_t hver; /* Hyper-Privileged Version Reg. */ + + /* * Instruction translation cache and Virtual->Physical->Host * address translation: @@ -240,6 +268,14 @@ #define SPARC_PSTATE_AG 0x001 /* Alternate Globals */ +/* Hyper-Privileged State Register (HPSTATE) bit definitions: */ +#define SPARC_HPSTATE_ID 0x800 +#define SPARC_HPSTATE_IBE 0x400 /* Instruction Break Enable */ +#define SPARC_HPSTATE_RED 0x020 /* Reset/Error/Debug state */ +#define SPARC_HPSTATE_HPRIV 0x004 /* Hyper-Privileged mode */ +#define SPARC_HPSTATE_TLZ 0x001 /* Trap Level Zero trap enable */ + + /* Condition Code Register bit definitions: */ #define SPARC_CCR_XCC_MASK 0xf0 #define SPARC_CCR_XCC_SHIFT 4 @@ -302,10 +338,12 @@ /* cpu_sparc.c: */ int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib); +int sparc_run_instr(struct cpu *cpu); void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page); void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); +int sparc32_run_instr(struct cpu *cpu); void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, unsigned char *host_page, int writeflag, uint64_t paddr_page); void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); @@ -315,5 +353,9 @@ unsigned char *data, size_t len, int writeflag, int cache_flags); int sparc_cpu_family_init(struct cpu_family *); +/* memory_sparc.c: */ +int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr, + uint64_t *return_addr, int flags); + #endif /* CPU_SPARC_H */