/[gxemul]/trunk/src/include/cpu_sparc.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
ViewVC logotype

Diff of /trunk/src/include/cpu_sparc.h

Parent Directory Parent Directory | Revision Log Revision Log | View Patch Patch

revision 22 by dpavlin, Mon Oct 8 16:19:37 2007 UTC revision 36 by dpavlin, Mon Oct 8 16:21:34 2007 UTC
# Line 2  Line 2 
2  #define CPU_SPARC_H  #define CPU_SPARC_H
3    
4  /*  /*
5   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sparc.h,v 1.23 2006/02/13 04:23:25 debug Exp $   *  $Id: cpu_sparc.h,v 1.46 2007/03/16 18:49:06 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
# Line 40  struct cpu_family; Line 40  struct cpu_family;
40  /*  SPARC CPU types:  */  /*  SPARC CPU types:  */
41  struct sparc_cpu_type_def {  struct sparc_cpu_type_def {
42          char            *name;          char            *name;
43          int             bits;          int             v;                      /*  v8, v9 etc  */
44            int             h;                      /*  hypervisor? sun4v = 1  */
45            int             bits;                   /*  32 or 64  */
46            int             nwindows;               /*  usually 8 or more  */
47          int             icache_shift;          int             icache_shift;
48          int             ilinesize;          int             ilinesize;
49          int             iway;          int             iway;
# Line 52  struct sparc_cpu_type_def { Line 55  struct sparc_cpu_type_def {
55          int             l2way;          int             l2way;
56  };  };
57    
58    /*  NOTE/TODO: Maybe some of the types listed below as v8 are in
59        fact v7; I haven't had time to check. Also, the nwindows value is
60        just bogus.  */
61    /*  See http://www.sparc.com/standards/v8v9-numbers.html for
62        implementation numbers!  */
63    /*  Note/TODO: sun4v is listed as 10  */
64    
65  #define SPARC_CPU_TYPE_DEFS     {                                       \  #define SPARC_CPU_TYPE_DEFS     {                                       \
66          { "SPARCv7",    32, 14,5,4, 14,5,4, 0,0,0 },                    \          { "TMS390Z50",          8, 0, 32, 8, 14,5,2, 14,5,2,  0,0,0 },  \
67          { "SPARCv9",    64, 14,5,4, 14,5,4, 0,0,0 },                    \          { "MB86904",            8, 0, 32, 8, 14,5,2, 13,4,2,  0,0,0 },  \
68          { NULL,         0,  0,0,0,  0,0,0,  0,0,0 }                     \          { "MB86907",            8, 0, 32, 8, 14,5,2, 14,5,2, 19,5,1 },  \
69            { "UltraSPARC",         9, 0, 64, 8, 14,5,4, 14,5,4, 19,6,1 },  \
70            { "UltraSPARC-IIi",     9, 0, 64, 8, 15,5,2, 14,5,2, 21,6,1 },  \
71            { "UltraSPARC-II",      9, 0, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
72            { "T1",                 9, 1, 64, 8, 15,5,2, 14,5,2, 22,6,1 },  \
73            { NULL,                 0, 0,  0, 0,  0,0,0,  0,0,0,  0,0,0 }   \
74          }          }
75    
76    
# Line 68  struct sparc_cpu_type_def { Line 83  struct sparc_cpu_type_def {
83  #define SPARC_ADDR_TO_PAGENR(a)         ((a) >> (SPARC_IC_ENTRIES_SHIFT \  #define SPARC_ADDR_TO_PAGENR(a)         ((a) >> (SPARC_IC_ENTRIES_SHIFT \
84                                          + SPARC_INSTR_ALIGNMENT_SHIFT))                                          + SPARC_INSTR_ALIGNMENT_SHIFT))
85    
86    #define SPARC_L2N               17
87    #define SPARC_L3N               18      /*  4KB pages on 32-bit sparc,  */
88                                            /*  8KB pages on 64-bit?  TODO  */
89    
90  DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t)  DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,uint64_t)
91    DYNTRANS_MISC64_DECLARATIONS(sparc,SPARC,uint8_t)
92    
93  #define SPARC_MAX_VPH_TLB_ENTRIES               128  #define SPARC_MAX_VPH_TLB_ENTRIES               128
94    
95    
96  #define N_SPARC_REG             32  #define N_SPARC_REG             32
97    #define N_SPARC_GLOBAL_REG      8
98    #define N_SPARC_INOUT_REG       8
99    #define N_SPARC_LOCAL_REG       8
100  #define SPARC_REG_NAMES {                               \  #define SPARC_REG_NAMES {                               \
101          "g0","g1","g2","g3","g4","g5","g6","g7",        \          "g0","g1","g2","g3","g4","g5","g6","g7",        \
102          "o0","o1","o2","o3","o4","o5","sp","o7",        \          "o0","o1","o2","o3","o4","o5","sp","o7",        \
103          "l0","l1","l2","l3","l4","l5","l6","l7",        \          "l0","l1","l2","l3","l4","l5","l6","l7",        \
104          "i0","i1","i2","i3","i4","i5","fp","i7" }          "i0","i1","i2","i3","i4","i5","fp","i7" }
105    
106    #define SPARC_ZEROREG           0       /*  g0  */
107    #define SPARC_REG_G0            0
108    #define SPARC_REG_G1            1
109    #define SPARC_REG_G2            2
110    #define SPARC_REG_G3            3
111    #define SPARC_REG_G4            4
112    #define SPARC_REG_G5            5
113    #define SPARC_REG_G6            6
114    #define SPARC_REG_G7            7
115    #define SPARC_REG_O0            8
116    #define SPARC_REG_O1            9
117    #define SPARC_REG_O2            10
118    #define SPARC_REG_O3            11
119    #define SPARC_REG_O4            12
120    #define SPARC_REG_O5            13
121    #define SPARC_REG_O6            14
122    #define SPARC_REG_O7            15
123    #define SPARC_REG_L0            16
124    #define SPARC_REG_L1            17
125    #define SPARC_REG_L2            18
126    #define SPARC_REG_L3            19
127    #define SPARC_REG_L4            20
128    #define SPARC_REG_L5            21
129    #define SPARC_REG_L6            22
130    #define SPARC_REG_L7            23
131    #define SPARC_REG_I0            24
132    #define SPARC_REG_I1            25
133    #define SPARC_REG_I2            26
134    #define SPARC_REG_I3            27
135    #define SPARC_REG_I4            28
136    #define SPARC_REG_I5            29
137    #define SPARC_REG_I6            30
138    #define SPARC_REG_I7            31
139    
140    /*  Privileged registers:  */
141    #define N_SPARC_PREG            32
142    #define SPARC_PREG_NAMES        {                                       \
143            "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",   \
144            "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",  \
145            "wstate", "fq", "reserved16", "reserved17", "reserved18", \
146            "reserved19", "reserved20", "reserved21", "reserved22", \
147            "reserved23", "reserved24", "reserved25", "reserved26", \
148            "reserved27", "reserved28", "reserved29", "reserved30", \
149            "ver" }
150    
151  #define N_SPARC_BRANCH_TYPES    16  #define N_SPARC_BRANCH_TYPES    16
152  #define SPARC_BRANCH_NAMES {                                            \  #define SPARC_BRANCH_NAMES {                                            \
153          "bn", "be",  "ble", "bl",  "bleu", "bcs", "bneg", "bvs",        \          "bn", "be",  "ble", "bl",  "bleu", "bcs", "bneg", "bvs",        \
154          "b",  "bne", "bg",  "bge", "bgu",  "bcc", "bpos", "bvc"  }          "ba", "bne", "bg",  "bge", "bgu",  "bcc", "bpos", "bvc"  }
155    
156  #define N_SPARC_REGBRANCH_TYPES 8  #define N_SPARC_REGBRANCH_TYPES 8
157  #define SPARC_REGBRANCH_NAMES {                                         \  #define SPARC_REGBRANCH_NAMES {                                         \
# Line 96  DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,u Line 164  DYNTRANS_MISC_DECLARATIONS(sparc,SPARC,u
164          "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\          "addcc","andcc","orcc","xorcc","subcc","andncc","orncc","xnorcc",\
165          "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\          "addxcc","[25]","umulcc","smulcc","subxcc","[29]","udivcc","sdivcc",\
166          "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\          "taddcc","tsubcc","taddcctv","tsubcctv","mulscc","sll","srl","sra",\
167          "[40]","[41]","[42]","[43]", "[44]","[45]","[46]","movre",      \          "rd" /* membar/stbar on sparcv9 */,                             \
168          "[48]","[49]","[50]","[51]", "[52]","[53]","[54]","[55]",       \          "rd" /* rd psr on pre-sparcv9 */, "rdpr","rd",                  \
169            "[44]","[45]","popc","movre",    \
170            "wr*","saved/restored","wrpr","[51]", "[52]","[53]","[54]","[55]",\
171          "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" }          "jmpl", "rett", "trap", "flush", "save", "restore", "[62]","[63]" }
172    
173  #define N_LOADSTORE_TYPES       64  #define N_LOADSTORE_TYPES       64
174  #define SPARC_LOADSTORE_NAMES {                                         \  #define SPARC_LOADSTORE_NAMES {                                         \
175          "ld","ldub","lduh","ldd", "st","stb","sth","std",               \          "lduw","ldub","lduh","ldd", "st","stb","sth","std",             \
176          "[8]","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",        \          "ldsw","ldsb","ldsh","ldx", "[12]","ldstub","stx","swap",       \
177          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \          "lda","lduba","lduha","ldda", "sta","stba","stha","stda",       \
178          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \          "[24]","ldsba","ldsha","ldxa", "[28]","ldstuba","stxa","swapa",  \
179          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \          "ldf","ldfsr","[34]","lddf", "stf","stfsr","stdfq","stdf",      \
180          "[40]","[41]","[42]","[43]", "[44]","[45]","[46]","[47]",       \          "[40]","[41]","[42]","[43]", "[44]","prefetch","[46]","[47]",   \
181          "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf",      \          "ldc","ldcsr","[50]","lddc", "stc","stcsr","scdfq","scdf",      \
182          "[56]","[57]","[58]","[59]", "[60]","[61]","casxa","[63]" }          "[56]","[57]","[58]","[59]", "[60]","prefetcha","casxa","[63]" }
183    
184    
185    /*  Max number of Trap Levels, Global Levels, and Register Windows:  */
186    #define MAXTL                   6
187    #define MAXGL                   7
188    #define N_REG_WINDOWS           8
189    
190    
191  struct sparc_cpu {  struct sparc_cpu {
192          struct sparc_cpu_type_def cpu_type;          struct sparc_cpu_type_def cpu_type;
193    
194            /*  Registers in the Current Window:  */
195          uint64_t        r[N_SPARC_REG];          uint64_t        r[N_SPARC_REG];
196          uint64_t        zero;                   /*  for dyntrans; ALWAYS zero */  
197            uint64_t        r_inout[N_REG_WINDOWS][N_SPARC_INOUT_REG];
198            uint64_t        r_local[N_REG_WINDOWS][N_SPARC_LOCAL_REG];
199    
200            uint64_t        r_global[MAXGL+1][N_SPARC_GLOBAL_REG];
201    
202            uint64_t        scratch;
203    
204            /*  Pre-SPARCv9 specific:  */
205            uint32_t        psr;            /*  Processor State Register  */
206            uint32_t        tbr;            /*  Trap base register  */
207            uint32_t        wim;            /*  Window invalid mask  */
208    
209            /*  SPARCv9 etc.:  */
210            uint64_t        pstate;         /*  Processor State Register  */
211            uint64_t        y;              /*  Y-reg (only low 32-bits used)  */
212            uint64_t        fprs;           /*  Floating Point Register Status  */
213            uint64_t        tick;           /*  Tick Register  */
214            uint64_t        tick_cmpr;      /*  Tick Compare Register (?)  */
215            uint64_t        ver;            /*  Version register  */
216    
217            uint8_t         cwp;            /*  Current Window Pointer  */
218            uint8_t         cansave;        /*  CANSAVE register  */
219            uint8_t         canrestore;     /*  CANRESTORE register  */
220            uint8_t         otherwin;       /*  OTHERWIN register  */
221            uint8_t         cleanwin;       /*  CLEANWIN register  */
222    
223            uint8_t         wstate;         /*  Window state  */
224    
225            uint8_t         ccr;            /*  Condition Code Register  */
226            uint8_t         asi;            /*  Address Space Identifier  */
227            uint8_t         tl;             /*  Trap Level Register  */
228            uint8_t         gl;             /*  Global Level Register  */
229            uint8_t         pil;            /*  Processor Interrupt Level Reg.  */
230    
231            uint64_t        tpc[MAXTL];     /*  Trap Program Counter  */
232            uint64_t        tnpc[MAXTL];    /*  Trap Next Program Counter  */
233            uint64_t        tstate[MAXTL];  /*  Trap State  */
234            uint32_t        ttype[MAXTL];   /*  Trap Type  */
235    
236            uint64_t        tba;            /*  Trap Base Address  */
237    
238            uint64_t        hpstate;        /*  Hyper-Privileged State Register  */
239            uint64_t        htstate[MAXTL]; /*  Hyper-Privileged Trap State  */
240            uint64_t        hintp;          /*  Hyper-Privileged InterruptPending */
241            uint64_t        htba;           /*  Hyper-Privileged Trap Base Addr  */
242            uint64_t        hver;           /*  Hyper-Privileged Version Reg.  */
243    
244    
245          /*          /*
# Line 129  struct sparc_cpu { Line 253  struct sparc_cpu {
253  };  };
254    
255    
256    /*  Processor State Register (PSTATE) bit definitions:  */
257    #define SPARC_PSTATE_PID1       0x800
258    #define SPARC_PSTATE_PID0       0x400
259    #define SPARC_PSTATE_CLE        0x200   /*  Current Little Endian  */
260    #define SPARC_PSTATE_TLE        0x100   /*  Trap Little Endian  */
261    #define SPARC_PSTATE_MM_MASK    0x0c0   /*  Memory Model (TODO)  */
262    #define SPARC_PSTATE_MM_SHIFT       6
263    #define SPARC_PSTATE_RED        0x020   /*  Reset/Error/Debug state  */
264    #define SPARC_PSTATE_PEF        0x010   /*  Enable Floating-point  */
265    #define SPARC_PSTATE_AM         0x008   /*  Address Mask  */
266    #define SPARC_PSTATE_PRIV       0x004   /*  Privileged Mode  */
267    #define SPARC_PSTATE_IE         0x002   /*  Interrupt Enable  */
268    #define SPARC_PSTATE_AG         0x001   /*  Alternate Globals  */
269    
270    
271    /*  Hyper-Privileged State Register (HPSTATE) bit definitions:  */
272    #define SPARC_HPSTATE_ID        0x800
273    #define SPARC_HPSTATE_IBE       0x400   /*  Instruction Break Enable  */
274    #define SPARC_HPSTATE_RED       0x020   /*  Reset/Error/Debug state  */
275    #define SPARC_HPSTATE_HPRIV     0x004   /*  Hyper-Privileged mode  */
276    #define SPARC_HPSTATE_TLZ       0x001   /*  Trap Level Zero trap enable  */
277    
278    
279    /*  Condition Code Register bit definitions:  */
280    #define SPARC_CCR_XCC_MASK      0xf0
281    #define SPARC_CCR_XCC_SHIFT     4
282    #define SPARC_CCR_ICC_MASK      0x0f
283    #define SPARC_CCR_N             8
284    #define SPARC_CCR_Z             4
285    #define SPARC_CCR_V             2
286    #define SPARC_CCR_C             1
287    
288    
289    /*  CWP, CANSAVE, CANRESTORE, OTHERWIN, CLEANWIN bitmask:  */
290    #define SPARC_CWP_MASK          0x1f
291    
292    
293    /*  Window State bit definitions:  */
294    #define SPARC_WSTATE_OTHER_MASK         0x38
295    #define SPARC_WSTATE_OTHER_SHIFT        3
296    #define SPARC_WSTATE_NORMAL_MASK        0x07
297    
298    
299    /*  Tick Register bit definitions:  */
300    #define SPARC_TICK_NPT          (1ULL << 63)    /*  Non-privileged trap  */
301    
302    
303    /*  Addess Space Identifier bit definitions:  */
304    #define SPARC_ASI_RESTRICTED    0x80
305    
306    
307    /*  Trap Level Register bit definitions:  */
308    #define SPARC_TL_MASK           0x07
309    
310    
311    /*  Processor Interrupt Level Register bit definitions:  */
312    #define SPARC_PIL_MASK          0x0f
313    
314    
315    /*  Trap Type Register bit definitions:  */
316    #define SPARC_TTYPE_MASK        0x1ff
317    
318    
319    /*  Trap Base Address bit definitions:  */
320    #define SPARC_TBA_MASK          0xffffffffffff8000ULL
321    
322    
323    /*
324     *  Full address for a trap is:
325     *      TBA<bits 63..15> || X || TTYPE[TL] || 00000
326     *
327     *  where X is a bit which is true if TL>0 when the trap was taken.
328     */
329    
330    
331    /*  Version Register bit definitions:  */
332    #define SPARC_VER_MANUF_SHIFT   48
333    #define SPARC_VER_IMPL_SHIFT    32
334    #define SPARC_VER_MASK_SHIFT    24
335    #define SPARC_VER_MAXTL_SHIFT   8
336    #define SPARC_VER_MAXWIN_SHIFT  0
337    
338    
339  /*  cpu_sparc.c:  */  /*  cpu_sparc.c:  */
340    int sparc_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
341    int sparc_run_instr(struct cpu *cpu);
342  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
343          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
344  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
345  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
346    int sparc32_run_instr(struct cpu *cpu);
347  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sparc32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
348          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
349  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sparc32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
350  void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sparc32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
351    void sparc_init_64bit_dummy_tables(struct cpu *cpu);
352  int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
353          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
354  int sparc_cpu_family_init(struct cpu_family *);  int sparc_cpu_family_init(struct cpu_family *);
355    
356    /*  memory_sparc.c:  */
357    int sparc_translate_v2p(struct cpu *cpu, uint64_t vaddr,
358            uint64_t *return_addr, int flags);
359    
360    
361  #endif  /*  CPU_SPARC_H  */  #endif  /*  CPU_SPARC_H  */
Legend:
Removed from v.22  
changed lines
  Added in v.36
  ViewVC Help
Powered by ViewVC 1.1.26