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dpavlin |
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#ifndef CPU_SPARC_H |
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#define CPU_SPARC_H |
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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dpavlin |
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* $Id: cpu_sparc.h,v 1.12 2005/10/27 14:01:15 debug Exp $ |
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dpavlin |
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*/ |
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#include "misc.h" |
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struct cpu_family; |
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#define SPARC_N_IC_ARGS 3 |
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#define SPARC_INSTR_ALIGNMENT_SHIFT 2 |
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#define SPARC_IC_ENTRIES_SHIFT 10 |
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#define SPARC_IC_ENTRIES_PER_PAGE (1 << SPARC_IC_ENTRIES_SHIFT) |
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#define SPARC_PC_TO_IC_ENTRY(a) (((a)>>SPARC_INSTR_ALIGNMENT_SHIFT) \ |
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& (SPARC_IC_ENTRIES_PER_PAGE-1)) |
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#define SPARC_ADDR_TO_PAGENR(a) ((a) >> (SPARC_IC_ENTRIES_SHIFT \ |
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+ SPARC_INSTR_ALIGNMENT_SHIFT)) |
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struct sparc_instr_call { |
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void (*f)(struct cpu *, struct sparc_instr_call *); |
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size_t arg[SPARC_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct sparc_tc_physpage { |
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dpavlin |
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struct sparc_instr_call ics[SPARC_IC_ENTRIES_PER_PAGE + 1]; |
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dpavlin |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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dpavlin |
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int flags; |
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dpavlin |
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uint64_t physaddr; |
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}; |
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#define SPARC_N_VPH_ENTRIES 1048576 |
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#define SPARC_MAX_VPH_TLB_ENTRIES 256 |
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struct sparc_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint64_t vaddr_page; |
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uint64_t paddr_page; |
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}; |
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struct sparc_cpu { |
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/* TODO */ |
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uint64_t r_i[8]; |
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/* |
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* Instruction translation cache: |
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*/ |
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/* cur_ic_page is a pointer to an array of SPARC_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct sparc_tc_physpage *cur_physpage; |
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struct sparc_instr_call *cur_ic_page; |
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struct sparc_instr_call *next_ic; |
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/* |
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* Virtual -> physical -> host address translation: |
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* |
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* host_load and host_store point to arrays of SPARC_N_VPH_ENTRIES |
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* pointers (to host pages); phys_addr points to an array of |
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* SPARC_N_VPH_ENTRIES uint32_t. |
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*/ |
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struct sparc_vpg_tlb_entry vph_tlb_entry[SPARC_MAX_VPH_TLB_ENTRIES]; |
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unsigned char *host_load[SPARC_N_VPH_ENTRIES]; |
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unsigned char *host_store[SPARC_N_VPH_ENTRIES]; |
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uint32_t phys_addr[SPARC_N_VPH_ENTRIES]; |
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struct sparc_tc_physpage *phys_page[SPARC_N_VPH_ENTRIES]; |
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uint32_t phystranslation[SPARC_N_VPH_ENTRIES/32]; |
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dpavlin |
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}; |
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/* cpu_sparc.c: */ |
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void sparc_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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dpavlin |
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void sparc_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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dpavlin |
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void sparc_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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dpavlin |
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int sparc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int sparc_cpu_family_init(struct cpu_family *); |
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#endif /* CPU_SPARC_H */ |