28 |
* SUCH DAMAGE. |
* SUCH DAMAGE. |
29 |
* |
* |
30 |
* |
* |
31 |
* $Id: cpu_sh.h,v 1.39 2007/04/04 19:59:24 debug Exp $ |
* $Id: cpu_sh.h,v 1.41 2007/04/28 09:19:34 debug Exp $ |
32 |
* |
* |
33 |
* Note: Many things here are SH4-specific, so it probably doesn't work |
* Note: Many things here are SH4-specific, so it probably doesn't work |
34 |
* for SH3 emulation. |
* for SH3 emulation. |
152 |
/* Cached and calculated values: */ |
/* Cached and calculated values: */ |
153 |
uint8_t int_prio_and_pending[0x1000 / 0x20]; |
uint8_t int_prio_and_pending[0x1000 / 0x20]; |
154 |
int16_t int_to_assert; /* Calculated int to assert */ |
int16_t int_to_assert; /* Calculated int to assert */ |
155 |
int int_level; /* Calculated int level */ |
unsigned int int_level; /* Calculated int level */ |
156 |
|
|
157 |
/* Timer/clock functionality: */ |
/* Timer/clock functionality: */ |
158 |
int pclock; |
int pclock; |
163 |
uint32_t dmac_tcr[4]; |
uint32_t dmac_tcr[4]; |
164 |
uint32_t dmac_chcr[4]; |
uint32_t dmac_chcr[4]; |
165 |
|
|
166 |
|
/* PCI controller: */ |
167 |
|
struct pci_data *pcic_pcibus; |
168 |
|
|
169 |
|
|
170 |
/* |
/* |
171 |
* Instruction translation cache and Virtual->Physical->Host |
* Instruction translation cache and Virtual->Physical->Host |
173 |
*/ |
*/ |
174 |
DYNTRANS_ITC(sh) |
DYNTRANS_ITC(sh) |
175 |
VPH_TLBS(sh,SH) |
VPH_TLBS(sh,SH) |
176 |
VPH32(sh,SH,uint64_t,uint8_t) |
VPH32(sh,SH,uint32_t,uint8_t) |
177 |
}; |
}; |
178 |
|
|
179 |
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|