/[gxemul]/trunk/src/include/cpu_sh.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 18 by dpavlin, Mon Oct 8 16:19:11 2007 UTC revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC
# Line 2  Line 2 
2  #define CPU_SH_H  #define CPU_SH_H
3    
4  /*  /*
5   *  Copyright (C) 2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2005-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_sh.h,v 1.7 2005/10/27 14:01:15 debug Exp $   *  $Id: cpu_sh.h,v 1.33 2006/10/27 15:51:37 debug Exp $
32     *
33     *  Note: Many things here are SH4-specific, so it probably doesn't work
34     *        for SH3 emulation.
35   */   */
36    
37  #include "misc.h"  #include "misc.h"
38    #include "sh4_cpu.h"
39    
40    
41  struct cpu_family;  struct cpu_family;
42    
43    /*  SH CPU types:  */
44    struct sh_cpu_type_def {
45            char            *name;
46            int             bits;
47            int             arch;
48            uint32_t        pvr;
49            uint32_t        prr;
50    };
51    
52    #define SH_CPU_TYPE_DEFS                {           \
53            { "SH7750", 32, 4, SH4_PVR_SH7750, 0     }, \
54            { "SH5",    64, 5, 0,              0     }, \
55            { NULL,      0, 0, 0,              0     }  }
56    
57    
58    /*
59     *  TODO: Figure out how to nicely support multiple instruction encodings!
60     *  For now, I'm reverting this to SH4. SH5 will have to wait until later.
61     */
62    
63  #define SH_N_IC_ARGS                    3  #define SH_N_IC_ARGS                    2       /*  3 for SH5/SH64  */
64  #define SH_INSTR_ALIGNMENT_SHIFT        2  #define SH_INSTR_ALIGNMENT_SHIFT        1       /*  2 for SH5/SH64  */
65  #define SH_IC_ENTRIES_SHIFT             10  #define SH_IC_ENTRIES_SHIFT             11      /*  10 for SH5/SH64  */
66  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)  #define SH_IC_ENTRIES_PER_PAGE          (1 << SH_IC_ENTRIES_SHIFT)
67  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \  #define SH_PC_TO_IC_ENTRY(a)            (((a)>>SH_INSTR_ALIGNMENT_SHIFT) \
68                                          & (SH_IC_ENTRIES_PER_PAGE-1))                                          & (SH_IC_ENTRIES_PER_PAGE-1))
69  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \  #define SH_ADDR_TO_PAGENR(a)            ((a) >> (SH_IC_ENTRIES_SHIFT \
70                                          + SH_INSTR_ALIGNMENT_SHIFT))                                          + SH_INSTR_ALIGNMENT_SHIFT))
71    
72  struct sh_instr_call {  DYNTRANS_MISC_DECLARATIONS(sh,SH,uint32_t)
         void    (*f)(struct cpu *, struct sh_instr_call *);  
         size_t  arg[SH_N_IC_ARGS];  
 };  
73    
74  /*  Translation cache struct for each physical page:  */  #define SH_MAX_VPH_TLB_ENTRIES          128
 struct sh_tc_physpage {  
         struct sh_instr_call ics[SH_IC_ENTRIES_PER_PAGE + 1];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
75    
 #define SH_N_VPH_ENTRIES                1048576  
76    
77  #define SH_MAX_VPH_TLB_ENTRIES          256  #define SH_N_GPRS               16
78  struct sh_vpg_tlb_entry {  #define SH_N_GPRS_BANKED        8
79          int             valid;  #define SH_N_FPRS               16
         int             writeflag;  
         int64_t         timestamp;  
         unsigned char   *host_page;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
 };  
80    
81  struct sh_cpu {  #define SH_N_ITLB_ENTRIES       4
82          int             bits;  #define SH_N_UTLB_ENTRIES       64
         int             compact;  
83    
         uint64_t        r[64];  
84    
85    struct sh_cpu {
86            struct sh_cpu_type_def cpu_type;
87    
88          /*          /*  compact = 1 if currently executing 16-bit long opcodes  */
89           *  Instruction translation cache:          int             compact;
          */  
90    
91          /*  cur_ic_page is a pointer to an array of SH_IC_ENTRIES_PER_PAGE          /*  General Purpose Registers:  */
92              instruction call entries. next_ic points to the next such          uint32_t        r[SH_N_GPRS];
93              call to be executed.  */          uint32_t        r_bank[SH_N_GPRS_BANKED];
94          struct sh_tc_physpage   *cur_physpage;  
95          struct sh_instr_call    *cur_ic_page;          /*  Floating-Point Registers:  */
96          struct sh_instr_call    *next_ic;          uint32_t        fr[SH_N_FPRS];
97            uint32_t        xf[SH_N_FPRS];  /*  "Other bank."  */
98    
99            uint32_t        mach;           /*  Multiply-Accumulate High  */
100            uint32_t        macl;           /*  Multiply-Accumulate Low  */
101            uint32_t        pr;             /*  Procedure Register  */
102            uint32_t        fpscr;          /*  Floating-point Status/Control  */
103            uint32_t        fpul;           /*  Floating-point Communication Reg  */
104            uint32_t        sr;             /*  Status Register  */
105            uint32_t        ssr;            /*  Saved Status Register  */
106            uint32_t        spc;            /*  Saved PC  */
107            uint32_t        gbr;            /*  Global Base Register  */
108            uint32_t        vbr;            /*  Vector Base Register  */
109            uint32_t        sgr;            /*  Saved General Register  */
110            uint32_t        dbr;            /*  Debug Base Register  */
111    
112            /*  Cache control:  */
113            uint32_t        ccr;            /*  Cache Control Register  */
114            uint32_t        qacr0;          /*  Queue Address Control Register 0  */
115            uint32_t        qacr1;          /*  Queue Address Control Register 1  */
116    
117            /*  MMU/TLB registers:  */
118            uint32_t        pteh;           /*  Page Table Entry High  */
119            uint32_t        ptel;           /*  Page Table Entry Low  */
120            uint32_t        ptea;           /*  Page Table Entry A  */
121            uint32_t        ttb;            /*  Translation Table Base  */
122            uint32_t        tea;            /*  TLB Exception Address Register  */
123            uint32_t        mmucr;          /*  MMU Control Register  */
124            uint32_t        itlb_hi[SH_N_ITLB_ENTRIES];
125            uint32_t        itlb_lo[SH_N_ITLB_ENTRIES];
126            uint32_t        utlb_hi[SH_N_UTLB_ENTRIES];
127            uint32_t        utlb_lo[SH_N_UTLB_ENTRIES];
128    
129            /*  Exception handling:  */
130            uint32_t        tra;            /*  TRAPA Exception Register  */
131            uint32_t        expevt;         /*  Exception Event Register  */
132            uint32_t        intevt;         /*  Interrupt Event Register  */
133    
134            /*  Interrupt controller:  */
135            uint16_t        intc_ipra;      /*  Interrupt Priority Registers  */
136            uint16_t        intc_iprb;
137            uint16_t        intc_iprc;
138            int16_t         int_to_assert;  /*  Calculated int to assert  */
139            int             int_level;      /*  Calculated int level  */
140            uint32_t        int_pending[0x1000 / 0x20 / (sizeof(uint32_t)*8)];
141    
142            /*  Timer/clock functionality:  */
143            int             pclock;
144    
145    
146          /*          /*
147           *  Virtual -> physical -> host address translation:           *  Instruction translation cache and Virtual->Physical->Host
148           *           *  address translation:
          *  host_load and host_store point to arrays of SH_N_VPH_ENTRIES  
          *  pointers (to host pages); phys_addr points to an array of  
          *  SH_N_VPH_ENTRIES uint32_t.  
149           */           */
150            DYNTRANS_ITC(sh)
151            VPH_TLBS(sh,SH)
152            VPH32(sh,SH,uint64_t,uint8_t)
153    };
154    
         struct sh_vpg_tlb_entry  vph_tlb_entry[SH_MAX_VPH_TLB_ENTRIES];  
         unsigned char            *host_load[SH_N_VPH_ENTRIES];  
         unsigned char            *host_store[SH_N_VPH_ENTRIES];  
         uint32_t                 phys_addr[SH_N_VPH_ENTRIES];  
         struct sh_tc_physpage    *phys_page[SH_N_VPH_ENTRIES];  
155    
156          uint32_t                 phystranslation[SH_N_VPH_ENTRIES/32];  /*  Status register bits:  */
157  };  #define SH_SR_T                 0x00000001      /*  True/false  */
158    #define SH_SR_S                 0x00000002      /*  Saturation  */
159    #define SH_SR_IMASK             0x000000f0      /*  Interrupt mask  */
160    #define SH_SR_IMASK_SHIFT               4
161    #define SH_SR_Q                 0x00000100      /*  State for Divide Step  */
162    #define SH_SR_M                 0x00000200      /*  State for Divide Step  */
163    #define SH_SR_FD                0x00008000      /*  FPU Disable  */
164    #define SH_SR_BL                0x10000000      /*  Exception/Interrupt Block */
165    #define SH_SR_RB                0x20000000      /*  Register Bank 0/1  */
166    #define SH_SR_MD                0x40000000      /*  Privileged Mode  */
167    
168    /*  Floating-point status/control register bits:  */
169    #define SH_FPSCR_RM_MASK        0x00000003      /*  Rounding Mode  */
170    #define    SH_FPSCR_RM_NEAREST         0x0      /*  Round to nearest  */
171    #define    SH_FPSCR_RM_ZERO            0x1      /*  Round to zero  */
172    #define SH_FPSCR_INEXACT        0x00000004      /*  Inexact exception  */
173    #define SH_FPSCR_UNDERFLOW      0x00000008      /*  Underflow exception  */
174    #define SH_FPSCR_OVERFLOW       0x00000010      /*  Overflow exception  */
175    #define SH_FPSCR_DIV_BY_ZERO    0x00000020      /*  Div by zero exception  */
176    #define SH_FPSCR_INVALID        0x00000040      /*  Invalid exception  */
177    #define SH_FPSCR_EN_INEXACT     0x00000080      /*  Inexact enable  */
178    #define SH_FPSCR_EN_UNDERFLOW   0x00000100      /*  Underflow enable  */
179    #define SH_FPSCR_EN_OVERFLOW    0x00000200      /*  Overflow enable  */
180    #define SH_FPSCR_EN_DIV_BY_ZERO 0x00000400      /*  Div by zero enable  */
181    #define SH_FPSCR_EN_INVALID     0x00000800      /*  Invalid enable  */
182    #define SH_FPSCR_CAUSE_INEXACT  0x00001000      /*  Cause Inexact  */
183    #define SH_FPSCR_CAUSE_UNDERFLOW 0x00002000     /*  Cause Underflow  */
184    #define SH_FPSCR_CAUSE_OVERFLOW 0x00004000      /*  Cause Overflow  */
185    #define SH_FPSCR_CAUSE_DIVBY0   0x00008000      /*  Cause Div by 0  */
186    #define SH_FPSCR_CAUSE_INVALID  0x00010000      /*  Cause Invalid  */
187    #define SH_FPSCR_CAUSE_ERROR    0x00020000      /*  Cause Error  */
188    #define SH_FPSCR_DN_ZERO        0x00040000      /*  Denormalization Mode  */
189    #define SH_FPSCR_PR             0x00080000      /*  Double-Precision Mode  */
190    #define SH_FPSCR_SZ             0x00100000      /*  Double-Precision Size  */
191    #define SH_FPSCR_FR             0x00200000      /*  Register Bank Select  */
192    
193    
194  /*  cpu_sh.c:  */  /*  cpu_sh.c:  */
195    int sh_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
196    int sh_run_instr(struct cpu *cpu);
197  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
198          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
199  void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sh_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
200  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
201    int sh32_run_instr(struct cpu *cpu);
202  void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void sh32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
203          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
204  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
205  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void sh32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
206    void sh_init_64bit_dummy_tables(struct cpu *cpu);
207  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int sh_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
208          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
209  int sh_cpu_family_init(struct cpu_family *);  int sh_cpu_family_init(struct cpu_family *);
210    
211    void sh_update_sr(struct cpu *cpu, uint32_t new_sr);
212    void sh_exception(struct cpu *cpu, int expevt, int intevt, uint32_t vaddr);
213    
214    /*  memory_sh.c:  */
215    int sh_translate_v2p(struct cpu *cpu, uint64_t vaddr,
216            uint64_t *return_addr, int flags);
217    
218    
219  #endif  /*  CPU_SH_H  */  #endif  /*  CPU_SH_H  */
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