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#ifndef CPU_PPC_H |
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#define CPU_PPC_H |
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|
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/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* 1. Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* 3. The name of the author may not be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
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* SUCH DAMAGE. |
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* |
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* |
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* $Id: cpu_ppc.h,v 1.22 2005/03/08 22:58:58 debug Exp $ |
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*/ |
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|
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#include "misc.h" |
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|
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|
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struct cpu_family; |
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|
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#define MODE_PPC 0 |
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#define MODE_POWER 1 |
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|
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/* PPC CPU types: */ |
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struct ppc_cpu_type_def { |
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char *name; |
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int bits; |
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int flags; |
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int icache_shift; |
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int iway; |
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int dcache_shift; |
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int dway; |
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int l2cache_shift; |
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int l2way; |
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int altivec; |
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|
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/* TODO: POWER vs PowerPC? */ |
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}; |
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|
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/* Flags: */ |
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#define PPC_NOFP 1 |
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/* TODO: Most of these just bogus */ |
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|
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#define PPC_CPU_TYPE_DEFS { \ |
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{ "PPC405GP", 32, PPC_NOFP, 15, 2, 15, 2, 20, 1, 0 }, \ |
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{ "PPC603e", 32, 0, 14, 4, 14, 4, 0, 0, 0 }, \ |
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{ "MPC7400", 32, 0, 15, 2, 15, 2, 19, 1, 1 }, \ |
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{ "PPC750", 32, 0, 15, 2, 15, 2, 20, 1, 0 }, \ |
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{ "G4e", 32, 0, 15, 8, 15, 8, 18, 8, 1 }, \ |
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{ "PPC970", 64, 0, 16, 1, 15, 2, 19, 1, 1 }, \ |
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{ NULL, 0, 0, 0,0, 0,0, 0,0, 0 } \ |
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}; |
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|
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#define PPC_NGPRS 32 |
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#define PPC_NFPRS 32 |
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|
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struct ppc_cpu { |
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struct ppc_cpu_type_def cpu_type; |
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|
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int trace_tree_depth; |
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|
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uint64_t of_emul_addr; |
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uint64_t pc_last; |
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|
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int mode; /* MODE_PPC or MODE_POWER */ |
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int bits; /* 32 or 64 */ |
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|
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uint32_t cr; /* Condition Register */ |
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uint32_t fpscr; /* FP Status and Control Register */ |
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uint64_t lr; /* Link Register */ |
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uint64_t ctr; /* Count Register */ |
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uint64_t gpr[PPC_NGPRS]; /* General Purpose Registers */ |
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uint64_t xer; /* FP Exception Register */ |
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uint64_t fpr[PPC_NFPRS]; /* Floating-Point Registers */ |
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|
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uint32_t tbl; /* Time Base Lower */ |
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uint32_t tbu; /* Time Base Upper */ |
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uint32_t dec; /* Decrementer */ |
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uint32_t hdec; /* Hypervisor Decrementer */ |
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uint64_t ssr0; /* Machine status save/restore |
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register 0 */ |
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uint64_t ssr1; /* Machine status save/restore |
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register 1 */ |
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uint64_t msr; /* Machine state register */ |
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uint64_t sprg0; /* Special Purpose Register G0 */ |
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uint64_t sprg1; /* Special Purpose Register G1 */ |
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uint64_t sprg2; /* Special Purpose Register G2 */ |
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uint64_t sprg3; /* Special Purpose Register G3 */ |
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uint32_t pvr; /* Processor Version Register */ |
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uint32_t pir; /* Processor ID */ |
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}; |
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|
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|
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/* Machine status word bits: (according to Book 3) */ |
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#define PPC_MSR_SF (1ULL << 63) /* Sixty-Four-Bit Mode */ |
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/* bits 62..61 are reserved */ |
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#define PPC_MSR_HV (1ULL << 60) /* Hypervisor */ |
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/* bits 59..17 are reserved */ |
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#define PPC_MSR_ILE (1 << 16) /* Interrupt Little-Endian Mode */ |
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#define PPC_MSR_EE (1 << 15) /* External Interrupt Enable */ |
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#define PPC_MSR_PR (1 << 14) /* Problem State */ |
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#define PPC_MSR_FP (1 << 13) /* Floating-Point Available */ |
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#define PPC_MSR_ME (1 << 12) /* Machine Check Interrupt Enable */ |
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#define PPC_MSR_FE0 (1 << 11) /* Floating-Point Exception Mode 0 */ |
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#define PPC_MSR_SE (1 << 10) /* Single-Step Trace Enable */ |
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#define PPC_MSR_BE (1 << 9) /* Branch Trace Enable */ |
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#define PPC_MSR_FE1 (1 << 8) /* Floating-Point Exception Mode 1 */ |
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#define PPC_MSR_IR (1 << 5) /* Instruction Relocate */ |
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#define PPC_MSR_DR (1 << 4) /* Data Relocate */ |
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#define PPC_MSR_PMM (1 << 2) /* Performance Monitor Mark */ |
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#define PPC_MSR_RI (1 << 1) /* Recoverable Interrupt */ |
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#define PPC_MSR_LE (1) /* Little-Endian Mode */ |
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|
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/* XER bits: */ |
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#define PPC_XER_SO (1 << 31) /* Summary Overflow */ |
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#define PPC_XER_OV (1 << 30) /* Overflow */ |
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#define PPC_XER_CA (1 << 29) /* Carry */ |
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|
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|
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/* cpu_ppc.c: */ |
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struct cpu *ppc_cpu_new(struct memory *mem, struct machine *machine, |
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int cpu_id, char *cpu_type_name); |
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void ppc_cpu_show_full_statistics(struct machine *m); |
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void ppc_cpu_register_match(struct machine *m, char *name, |
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int writeflag, uint64_t *valuep, int *match_register); |
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void ppc_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs); |
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int ppc_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr, |
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int running, uint64_t addr, int bintrans); |
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int ppc_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr); |
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int ppc_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr); |
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int ppc_cpu_run(struct emul *emul, struct machine *machine); |
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void ppc_cpu_dumpinfo(struct cpu *cpu); |
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void ppc_cpu_list_available_types(void); |
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int ppc_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int ppc_cpu_family_init(struct cpu_family *); |
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|
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|
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#endif /* CPU_PPC_H */ |