/[gxemul]/trunk/src/include/cpu_mips.h
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revision 10 by dpavlin, Mon Oct 8 16:18:27 2007 UTC revision 32 by dpavlin, Mon Oct 8 16:20:58 2007 UTC
# Line 2  Line 2 
2  #define CPU_MIPS_H  #define CPU_MIPS_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2005  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.16 2005/06/26 22:23:43 debug Exp $   *  $Id: cpu_mips.h,v 1.50 2006/10/14 23:47:37 debug Exp $
32   */   */
33    
34  #include "misc.h"  #include "misc.h"
35    
 /*    
  *  ENABLE_MIPS16 should be defined on the cc commandline using -D, if you  
  *  want it. (This is done by ./configure --mips16)  
  */  
 /*  #define MFHILO_DELAY  */  
   
36  struct cpu_family;  struct cpu_family;
37  struct emul;  struct emul;
38  struct machine;  struct machine;
39    struct timer;
40    
41  /*  /*
42   *  CPU type definitions:  See mips_cpu_types.h.   *  CPU type definitions:  See mips_cpu_types.h.
# Line 55  struct mips_cpu_type_def { Line 50  struct mips_cpu_type_def {
50          char            exc_model;              /*  EXC3K or EXC4K  */          char            exc_model;              /*  EXC3K or EXC4K  */
51          char            mmu_model;              /*  MMU3K or MMU4K  */          char            mmu_model;              /*  MMU3K or MMU4K  */
52          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */          char            isa_level;              /*  1, 2, 3, 4, 5, 32, 64  */
53            char            isa_revision;           /*  1 or 2 (for MIPS32/64)  */
54          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */          int             nr_of_tlb_entries;      /*  32, 48, 64, ...  */
55          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */          char            instrs_per_cycle;       /*  simplified, 1, 2, or 4  */
56          int             default_picache;          int             picache;
57          int             default_pdcache;          int             pilinesize;
58          int             default_pilinesize;          int             piways;
59          int             default_pdlinesize;          int             pdcache;
60          int             default_scache;          int             pdlinesize;
61          int             default_slinesize;          int             pdways;
62            int             scache;
63            int             slinesize;
64            int             sways;
65  };  };
66    
67  #define INITIAL_PC                      0xffffffffbfc00000ULL  #define INITIAL_PC                      0xffffffffbfc00000ULL
# Line 71  struct mips_cpu_type_def { Line 70  struct mips_cpu_type_def {
70    
71  /*  /*
72   *  Coproc 0:   *  Coproc 0:
73     *
74     *  NOTE:
75     *      On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
76   */   */
77  #define N_MIPS_COPROC_REGS      32  #define N_MIPS_COPROC_REGS      32
78  struct mips_tlb {  struct mips_tlb {
# Line 84  struct mips_tlb { Line 86  struct mips_tlb {
86  /*  /*
87   *  Coproc 1:   *  Coproc 1:
88   */   */
89  #define N_MIPS_FCRS             32  /*  FPU control registers:  */
90    #define N_MIPS_FCRS                     32
91    #define MIPS_FPU_FCIR                   0
92    #define MIPS_FPU_FCCR                   25
93    #define MIPS_FPU_FCSR                   31
94    #define    MIPS_FCSR_FCC0_SHIFT            23
95    #define    MIPS_FCSR_FCC1_SHIFT            25
96    
97    #define N_VADDR_TO_TLB_INDEX_ENTRIES    (1 << 20)
98    
99  struct mips_coproc {  struct mips_coproc {
100          int             coproc_nr;          int             coproc_nr;
# Line 153  struct mips_coproc { Line 163  struct mips_coproc {
163  #define MIPS_GPR_FP             30              /*  fp  */  #define MIPS_GPR_FP             30              /*  fp  */
164  #define MIPS_GPR_RA             31              /*  ra  */  #define MIPS_GPR_RA             31              /*  ra  */
165    
 /*  Meaning of delay_slot:  */  
 #define NOT_DELAYED             0  
 #define DELAYED                 1  
 #define TO_BE_DELAYED           2  
   
166  #define N_HI6                   64  #define N_HI6                   64
167  #define N_SPECIAL               64  #define N_SPECIAL               64
168  #define N_REGIMM                32  #define N_REGIMM                32
169    
 /*  Number of "tiny" translation cache entries:  */  
 #define N_TRANSLATION_CACHE_INSTR       5  
 #define N_TRANSLATION_CACHE_DATA        5  
   
 struct translation_cache_entry {  
         int             wf;  
         uint64_t        vaddr_pfn;  
         uint64_t        paddr;  
 };  
   
 /*  This should be a value which the program counter  
     can "never" have:  */  
 #define PC_LAST_PAGE_IMPOSSIBLE_VALUE   3  
170    
171  /*  An "impossible" paddr:  */  /*  An "impossible" paddr:  */
172  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL
# Line 193  struct r4000_cache_line { Line 185  struct r4000_cache_line {
185          char            dummy;          char            dummy;
186  };  };
187    
 #define BINTRANS_DONT_RUN_NEXT          0x1000000  
 #define BINTRANS_N_MASK                 0x0ffffff  
188    
189  #define N_SAFE_BINTRANS_LIMIT_SHIFT     14  #ifdef ONEKPAGE
190  #define N_SAFE_BINTRANS_LIMIT   ((1 << (N_SAFE_BINTRANS_LIMIT_SHIFT - 1)) - 1)  #define MIPS_IC_ENTRIES_SHIFT           8
191    #else
192    #define MIPS_IC_ENTRIES_SHIFT           10
193    #endif
194    
195  #define N_BINTRANS_VADDR_TO_HOST        20  #define MIPS_N_IC_ARGS                  3
196    #define MIPS_INSTR_ALIGNMENT_SHIFT      2
197    #define MIPS_IC_ENTRIES_PER_PAGE        (1 << MIPS_IC_ENTRIES_SHIFT)
198    #define MIPS_PC_TO_IC_ENTRY(a)          (((a)>>MIPS_INSTR_ALIGNMENT_SHIFT) \
199                                            & (MIPS_IC_ENTRIES_PER_PAGE-1))
200    #define MIPS_ADDR_TO_PAGENR(a)          ((a) >> (MIPS_IC_ENTRIES_SHIFT \
201                                            + MIPS_INSTR_ALIGNMENT_SHIFT))
202    
203    #define MIPS_L2N                17
204    #define MIPS_L3N                18
205    
206    #define MIPS_MAX_VPH_TLB_ENTRIES        192
207    DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
208    DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
209    
 /*  Virtual to host address translation tables:  */  
 struct vth32_table {  
         void                    *haddr_entry[1024 * 2];  
         uint32_t                paddr_entry[1024];  
         uint32_t                *bintrans_chunks[1024];  
         struct vth32_table      *next_free;  
         int                     refcount;  
 };  
210    
211  struct mips_cpu {  struct mips_cpu {
212          struct mips_cpu_type_def cpu_type;          struct mips_cpu_type_def cpu_type;
213    
214          struct mips_coproc *coproc[N_MIPS_COPROCS];          /*  General purpose registers:  */
215            uint64_t        gpr[N_MIPS_GPRS];
216    
217          int             compare_register_set;          /*  Dummy destination register when writing to the zero register:  */
218            uint64_t        scratch;
219    
220          /*  Special purpose registers:  */          /*  Special purpose registers:  */
         uint64_t        pc_last;                /*  PC of last instruction   */  
221          uint64_t        hi;          uint64_t        hi;
222          uint64_t        lo;          uint64_t        lo;
223    
224          /*  General purpose registers:  */          /*  Coprocessors:  */
225          uint64_t        gpr[N_MIPS_GPRS];          struct mips_coproc *coproc[N_MIPS_COPROCS];
226            uint64_t        cop0_config_select1;
         /*  
          *  The translation_cached stuff is used to speed up the  
          *  most recent lookups into the TLB.  Whenever the TLB is  
          *  written to, translation_cached[] must be filled with zeros.  
          */  
 #ifdef USE_TINY_CACHE  
         struct translation_cache_entry  
                         translation_cache_instr[N_TRANSLATION_CACHE_INSTR];  
         struct translation_cache_entry  
                         translation_cache_data[N_TRANSLATION_CACHE_DATA];  
 #endif  
   
         /*  
          *  For faster memory lookup when running instructions:  
          *  
          *  Reading memory to load instructions is a very common thing in the  
          *  emulator, and an instruction is very often read from the address  
          *  following the previously executed instruction. That means that we  
          *  don't have to go through the TLB each time.  
          *  
          *  We then get the vaddr -> paddr translation for free. There is an  
          *  even better case when the paddr is a RAM address (as opposed to an  
          *  address in a memory mapped device). Then we can figure out the  
          *  address in the host's memory directly, and skip the paddr -> host  
          *  address calculation as well.  
          *  
          *  A modification to the TLB should set the virtual_page variable to  
          *  an "impossible" value, so that there won't be a hit on the next  
          *  instruction.  
          */  
         uint64_t        pc_last_virtual_page;  
         uint64_t        pc_last_physical_page;  
         unsigned char   *pc_last_host_4k_page;  
   
 #ifdef BINTRANS  
         int             dont_run_next_bintrans;  
         int             bintrans_instructions_executed;  /*  set to the  
                                 number of bintranslated instructions executed  
                                 when running a bintrans codechunk  */  
         int             pc_bintrans_paddr_valid;  
         uint64_t        pc_bintrans_paddr;  
         unsigned char   *pc_bintrans_host_4kpage;  
   
         /*  Chunk base address:  */  
         unsigned char   *chunk_base_address;  
   
         /*  This should work for 32-bit MIPS emulation:  */  
         struct vth32_table *vaddr_to_hostaddr_nulltable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_icachetable;  
         struct vth32_table *vaddr_to_hostaddr_r2k3k_dcachetable;  
         struct vth32_table **vaddr_to_hostaddr_table0_kernel;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_i;  
         struct vth32_table **vaddr_to_hostaddr_table0_cacheisol_d;  
         struct vth32_table **vaddr_to_hostaddr_table0_user;  
         struct vth32_table **vaddr_to_hostaddr_table0;  /*  should point to kernel or user  */  
         struct vth32_table *next_free_vth_table;  
   
         /*  For 64-bit (generic) emulation:  */  
         unsigned char   *(*fast_vaddr_to_hostaddr)(struct cpu *cpu,  
                             uint64_t vaddr, int writeflag);  
         int             bintrans_next_index;  
         int             bintrans_data_writable[N_BINTRANS_VADDR_TO_HOST];  
         uint64_t        bintrans_data_vaddr[N_BINTRANS_VADDR_TO_HOST];  
         unsigned char   *bintrans_data_hostpage[N_BINTRANS_VADDR_TO_HOST];  
   
         void            (*bintrans_load_32bit)(struct cpu *);   /*  Note: incorrect args  */  
         void            (*bintrans_store_32bit)(struct cpu *);  /*  Note: incorrect args  */  
         void            (*bintrans_jump_to_32bit_pc)(struct cpu *);  
         void            (*bintrans_simple_exception)(struct cpu *, int);  
         void            (*bintrans_fast_rfe)(struct cpu *);  
         void            (*bintrans_fast_eret)(struct cpu *);  
         void            (*bintrans_fast_tlbwri)(struct cpu *, int);  
         void            (*bintrans_fast_tlbpr)(struct cpu *, int);  
 #endif  
   
 #ifdef ENABLE_MIPS16  
         int             mips16;                 /*  non-zero if MIPS16 code is allowed  */  
         uint16_t        mips16_extend;          /*  set on 'extend' instructions to the entire 16-bit extend instruction  */  
 #endif  
   
 #ifdef ENABLE_INSTRUCTION_DELAYS  
         int             instruction_delay;  
 #endif  
227    
228          int             trace_tree_depth;          int             last_written_tlb_index;
229    
230          uint64_t        delay_jmpaddr;          /*  only used if delay_slot > 0  */          /*  Count/compare timer:  */
231          int             delay_slot;          int             compare_register_set;
232          int             nullify_next;           /*  set to 1 if next instruction          int             compare_interrupts_pending;
233                                                          is to be nullified  */          struct timer    *timer;
   
         /*  This is set to non-zero, if it is possible at all that an  
             interrupt will occur.  */  
         int             cached_interrupt_is_possible;  
   
         int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */  
         uint64_t        show_trace_addr;  
   
         int             last_was_jumptoself;  
         int             jump_to_self_reg;  
   
 #ifdef MFHILO_DELAY  
         int             mfhi_delay;     /*  instructions since last mfhi  */  
         int             mflo_delay;     /*  instructions since last mflo  */  
 #endif  
234    
235          int             rmw;            /*  Read-Modify-Write  */          int             rmw;            /*  Read-Modify-Write  */
236          int             rmw_len;        /*  Length of rmw modification  */          int             rmw_len;        /*  Length of rmw modification  */
237          uint64_t        rmw_addr;       /*  Address of rmw modification  */          uint64_t        rmw_addr;       /*  Address of rmw modification  */
238    
239          /*          /*
240           *  TODO:  The R5900 has 128-bit registers. I'm not really sure           *  NOTE:  The R5900 has 128-bit registers. I'm not really sure
241           *  whether they are used a lot or not, at least with code produced           *  whether they are used a lot or not, at least with code produced
242           *  with gcc they are not. An important case however is lq and sq           *  with gcc they are not. An important case however is lq and sq
243           *  (load and store of 128-bit values). These "upper halves" of R5900           *  (load and store of 128-bit values). These "upper halves" of R5900
244           *  quadwords can be used in those cases.           *  quadwords can be used in those cases.
245           *           *
246             *  hi1 and lo1 are the high 64-bit parts of the hi and lo registers.
247             *  sa is a 32-bit "shift amount" register.
248             *
249           *  TODO:  Generalize this.           *  TODO:  Generalize this.
250           */           */
251          uint64_t        gpr_quadhi[N_MIPS_GPRS];          uint64_t        gpr_quadhi[N_MIPS_GPRS];
252            uint64_t        hi1;
253            uint64_t        lo1;
254          /*          uint32_t        r5900_sa;
          *  Statistics:  
          */  
         long            stats_opcode[N_HI6];  
         long            stats__special[N_SPECIAL];  
         long            stats__regimm[N_REGIMM];  
         long            stats__special2[N_SPECIAL];  
255    
256          /*  Data and Instruction caches:  */          /*  Data and Instruction caches:  */
257          unsigned char   *cache[2];          unsigned char   *cache[2];
# Line 364  struct mips_cpu { Line 262  struct mips_cpu {
262          int             cache_mask[2];          int             cache_mask[2];
263          int             cache_miss_penalty[2];          int             cache_miss_penalty[2];
264    
265          /*  Other stuff:  */  
266          uint64_t        cop0_config_select1;          /*
267             *  Instruction translation cache and Virtual->Physical->Host
268             *  address translation:
269             */
270            DYNTRANS_ITC(mips)
271            VPH_TLBS(mips,MIPS)
272            VPH32(mips,MIPS,uint64_t,uint8_t)
273            VPH64(mips,MIPS,uint8_t)
274  };  };
275    
276    
277  /*  cpu_mips.c:  */  /*  cpu_mips.c:  */
278  void mips_cpu_show_full_statistics(struct machine *m);  int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
279  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
280  void mips_cpu_register_match(struct machine *m, char *name,  void mips_cpu_register_match(struct machine *m, char *name,
281          int writeflag, uint64_t *valuep, int *match_register);          int writeflag, uint64_t *valuep, int *match_register);
282  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
283  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
284          int running, uint64_t addr, int bintrans);          int running, uint64_t addr);
285  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);
286  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);  int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);
287  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
288          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
289          int vaddr_asid, int x_64);          int vaddr_asid, int x_64);
 void mips_cpu_cause_simple_exception(struct cpu *cpu, int exc_code);  
290  int mips_cpu_run(struct emul *emul, struct machine *machine);  int mips_cpu_run(struct emul *emul, struct machine *machine);
291  void mips_cpu_dumpinfo(struct cpu *cpu);  void mips_cpu_dumpinfo(struct cpu *cpu);
292  void mips_cpu_list_available_types(void);  void mips_cpu_list_available_types(void);
# Line 395  void mips_coproc_tlb_set_entry(struct cp Line 299  void mips_coproc_tlb_set_entry(struct cp
299          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,          uint64_t vaddr, uint64_t paddr0, uint64_t paddr1,
300          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,          int valid0, int valid1, int dirty0, int dirty1, int global, int asid,
301          int cachealgo0, int cachealgo1);          int cachealgo0, int cachealgo1);
 void update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  
         unsigned char *host_page, int writeflag, uint64_t paddr_page);  
 void clear_all_chunks_from_all_tables(struct cpu *cpu);  
 void mips_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);  
302  void coproc_register_read(struct cpu *cpu,  void coproc_register_read(struct cpu *cpu,
303          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);          struct mips_coproc *cp, int reg_nr, uint64_t *ptr, int select);
304  void coproc_register_write(struct cpu *cpu,  void coproc_register_write(struct cpu *cpu,
# Line 418  int memory_cache_R3000(struct cpu *cpu, Line 318  int memory_cache_R3000(struct cpu *cpu,
318  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
319          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
320    
321    int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
322  /*  mips16.c:  */          uint64_t *return_addr, int flags);
323  int mips16_to_32(struct cpu *cpu, unsigned char *instr16, unsigned char *instr);  int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
324            uint64_t *return_addr, int flags);
325    int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
326            uint64_t *return_addr, int flags);
327    int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
328            uint64_t *return_addr, int flags);
329    int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
330            uint64_t *return_addr, int flags);
331    
332    
333    /*  Dyntrans unaligned load/store:  */
334    void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
335            int is_left, int wlen, int store);
336    
337    
338    int mips_run_instr(struct cpu *cpu);
339    void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
340            unsigned char *host_page, int writeflag, uint64_t paddr_page);
341    void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
342    void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
343    int mips32_run_instr(struct cpu *cpu);
344    void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
345            unsigned char *host_page, int writeflag, uint64_t paddr_page);
346    void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
347    void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
348    
349    
350  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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