/[gxemul]/trunk/src/include/cpu_mips.h
This is repository of my old source code which isn't updated any more. Go to git.rot13.org for current projects!
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revision 24 by dpavlin, Mon Oct 8 16:19:56 2007 UTC revision 34 by dpavlin, Mon Oct 8 16:21:17 2007 UTC
# Line 2  Line 2 
2  #define CPU_MIPS_H  #define CPU_MIPS_H
3    
4  /*  /*
5   *  Copyright (C) 2003-2006  Anders Gavare.  All rights reserved.   *  Copyright (C) 2003-2007  Anders Gavare.  All rights reserved.
6   *   *
7   *  Redistribution and use in source and binary forms, with or without   *  Redistribution and use in source and binary forms, with or without
8   *  modification, are permitted provided that the following conditions are met:   *  modification, are permitted provided that the following conditions are met:
# Line 28  Line 28 
28   *  SUCH DAMAGE.   *  SUCH DAMAGE.
29   *   *
30   *   *
31   *  $Id: cpu_mips.h,v 1.42 2006/06/22 13:22:41 debug Exp $   *  $Id: cpu_mips.h,v 1.55 2007/02/07 18:58:32 debug Exp $
32   */   */
33    
34    #include "interrupt.h"
35  #include "misc.h"  #include "misc.h"
36    
37  struct cpu_family;  struct cpu_family;
38  struct emul;  struct emul;
39  struct machine;  struct machine;
40    struct timer;
41    
42  /*  /*
43   *  CPU type definitions:  See mips_cpu_types.h.   *  CPU type definitions:  See mips_cpu_types.h.
# Line 69  struct mips_cpu_type_def { Line 71  struct mips_cpu_type_def {
71    
72  /*  /*
73   *  Coproc 0:   *  Coproc 0:
74     *
75     *  NOTE:
76     *      On R3000, only hi and lo0 are used, and then only the lowest 32 bits.
77   */   */
78  #define N_MIPS_COPROC_REGS      32  #define N_MIPS_COPROC_REGS      32
79  struct mips_tlb {  struct mips_tlb {
# Line 90  struct mips_tlb { Line 95  struct mips_tlb {
95  #define    MIPS_FCSR_FCC0_SHIFT            23  #define    MIPS_FCSR_FCC0_SHIFT            23
96  #define    MIPS_FCSR_FCC1_SHIFT            25  #define    MIPS_FCSR_FCC1_SHIFT            25
97    
98    #define N_VADDR_TO_TLB_INDEX_ENTRIES    (1 << 20)
99    
100  struct mips_coproc {  struct mips_coproc {
101          int             coproc_nr;          int             coproc_nr;
102          uint64_t        reg[N_MIPS_COPROC_REGS];          uint64_t        reg[N_MIPS_COPROC_REGS];
# Line 161  struct mips_coproc { Line 168  struct mips_coproc {
168  #define N_SPECIAL               64  #define N_SPECIAL               64
169  #define N_REGIMM                32  #define N_REGIMM                32
170    
 /*******************************  OLD:  *****************************/  
171    
172  /*  An "impossible" paddr:  */  /*  An "impossible" paddr:  */
173  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL  #define IMPOSSIBLE_PADDR                0x1212343456566767ULL
# Line 180  struct r4000_cache_line { Line 186  struct r4000_cache_line {
186          char            dummy;          char            dummy;
187  };  };
188    
 /********************************************************************/  
189    
190  #ifdef ONEKPAGE  #ifdef ONEKPAGE
191  #define MIPS_IC_ENTRIES_SHIFT           8  #define MIPS_IC_ENTRIES_SHIFT           8
# Line 203  struct r4000_cache_line { Line 208  struct r4000_cache_line {
208  DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)  DYNTRANS_MISC_DECLARATIONS(mips,MIPS,uint64_t)
209  DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)  DYNTRANS_MISC64_DECLARATIONS(mips,MIPS,uint8_t)
210    
 #if 0  
 struct mips_instr_call {  
         void    (*f)(struct cpu *, struct mips_instr_call *);  
         size_t  arg[MIPS_N_IC_ARGS];  
 };  
   
 /*  Translation cache struct for each physical page:  */  
 struct mips_tc_physpage {  
         struct mips_instr_call ics[MIPS_IC_ENTRIES_PER_PAGE + 3];  
         uint32_t        next_ofs;       /*  or 0 for end of chain  */  
         int             flags;  
         uint64_t        physaddr;  
 };  
   
 struct mips_vpg_tlb_entry {  
         uint8_t         valid;  
         uint8_t         writeflag;  
         unsigned char   *host_page;  
         int64_t         timestamp;  
         uint64_t        vaddr_page;  
         uint64_t        paddr_page;  
 };  
 #endif  
   
 /********************************************************************/  
211    
212  struct mips_cpu {  struct mips_cpu {
213          struct mips_cpu_type_def cpu_type;          struct mips_cpu_type_def cpu_type;
214    
215          struct mips_coproc *coproc[N_MIPS_COPROCS];          /*  General purpose registers:  */
216            uint64_t        gpr[N_MIPS_GPRS];
217    
218          int             compare_register_set;          /*  Dummy destination register when writing to the zero register:  */
219            uint64_t        scratch;
220    
221          /*  Special purpose registers:  */          /*  Special purpose registers:  */
222          uint64_t        hi;          uint64_t        hi;
223          uint64_t        lo;          uint64_t        lo;
224    
225          /*  Dummy destination register when writing to the zero register:  */          /*  Coprocessors:  */
226          uint64_t        scratch;          struct mips_coproc *coproc[N_MIPS_COPROCS];
227            uint64_t        cop0_config_select1;
         /*  General purpose registers:  */  
         uint64_t        gpr[N_MIPS_GPRS];  
   
         int             nullify_next;           /*  set to 1 if next instruction  
                                                         is to be nullified  */  
228    
229          int             show_trace_delay;       /*  0=normal, > 0 = delay until show_trace  */          int             last_written_tlb_index;
         uint64_t        show_trace_addr;  
230    
231          int             last_was_jumptoself;          /*  Count/compare timer:  */
232          int             jump_to_self_reg;          int             compare_register_set;
233            int             compare_interrupts_pending;
234            struct interrupt irq_compare;
235            struct timer    *timer;
236    
237          int             rmw;            /*  Read-Modify-Write  */          int             rmw;            /*  Read-Modify-Write  */
238          int             rmw_len;        /*  Length of rmw modification  */          int             rmw_len;        /*  Length of rmw modification  */
# Line 276  struct mips_cpu { Line 255  struct mips_cpu {
255          uint64_t        lo1;          uint64_t        lo1;
256          uint32_t        r5900_sa;          uint32_t        r5900_sa;
257    
   
258          /*  Data and Instruction caches:  */          /*  Data and Instruction caches:  */
259          unsigned char   *cache[2];          unsigned char   *cache[2];
260          void            *cache_tags[2];          void            *cache_tags[2];
# Line 286  struct mips_cpu { Line 264  struct mips_cpu {
264          int             cache_mask[2];          int             cache_mask[2];
265          int             cache_miss_penalty[2];          int             cache_miss_penalty[2];
266    
         /*  Other stuff:  */  
         uint64_t        cop0_config_select1;  
   
   
         /*  NEW DYNTRANS:  */  
   
267    
268          /*          /*
269           *  Instruction translation cache and Virtual->Physical->Host           *  Instruction translation cache and Virtual->Physical->Host
# Line 305  struct mips_cpu { Line 277  struct mips_cpu {
277    
278    
279  /*  cpu_mips.c:  */  /*  cpu_mips.c:  */
280    void mips_cpu_interrupt_assert(struct interrupt *interrupt);
281    void mips_cpu_interrupt_deassert(struct interrupt *interrupt);
282  int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);  int mips_cpu_instruction_has_delayslot(struct cpu *cpu, unsigned char *ib);
283  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);  void mips_cpu_tlbdump(struct machine *m, int x, int rawflag);
284  void mips_cpu_register_match(struct machine *m, char *name,  void mips_cpu_register_match(struct machine *m, char *name,
# Line 312  void mips_cpu_register_match(struct mach Line 286  void mips_cpu_register_match(struct mach
286  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);  void mips_cpu_register_dump(struct cpu *cpu, int gprs, int coprocs);
287  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,  int mips_cpu_disassemble_instr(struct cpu *cpu, unsigned char *instr,
288          int running, uint64_t addr);          int running, uint64_t addr);
 int mips_cpu_interrupt(struct cpu *cpu, uint64_t irq_nr);  
 int mips_cpu_interrupt_ack(struct cpu *cpu, uint64_t irq_nr);  
289  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,  void mips_cpu_exception(struct cpu *cpu, int exccode, int tlb, uint64_t vaddr,
290          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,          /*  uint64_t pagemask,  */  int coproc_nr, uint64_t vaddr_vpn2,
291          int vaddr_asid, int x_64);          int vaddr_asid, int x_64);
# Line 348  int memory_cache_R3000(struct cpu *cpu, Line 320  int memory_cache_R3000(struct cpu *cpu,
320  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,  int mips_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
321          unsigned char *data, size_t len, int writeflag, int cache_flags);          unsigned char *data, size_t len, int writeflag, int cache_flags);
322    
323    int translate_v2p_mmu3k(struct cpu *cpu, uint64_t vaddr,
324            uint64_t *return_addr, int flags);
325    int translate_v2p_mmu8k(struct cpu *cpu, uint64_t vaddr,
326            uint64_t *return_addr, int flags);
327    int translate_v2p_mmu10k(struct cpu *cpu, uint64_t vaddr,
328            uint64_t *return_addr, int flags);
329    int translate_v2p_mmu4100(struct cpu *cpu, uint64_t vaddr,
330            uint64_t *return_addr, int flags);
331    int translate_v2p_generic(struct cpu *cpu, uint64_t vaddr,
332            uint64_t *return_addr, int flags);
333    
334    
335  /*  Dyntrans unaligned load/store:  */  /*  Dyntrans unaligned load/store:  */
336  void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,  void mips_unaligned_loadstore(struct cpu *cpu, struct mips_instr_call *ic,
337          int is_left, int wlen, int store);          int is_left, int wlen, int store);
338    
339    
340    int mips_run_instr(struct cpu *cpu);
341  void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void mips_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
342          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
343  void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void mips_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
344  void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void mips_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
345    int mips32_run_instr(struct cpu *cpu);
346  void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,  void mips32_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
347          unsigned char *host_page, int writeflag, uint64_t paddr_page);          unsigned char *host_page, int writeflag, uint64_t paddr_page);
348  void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);  void mips32_invalidate_translation_caches(struct cpu *cpu, uint64_t, int);
349  void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);  void mips32_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
 void mips_init_64bit_dummy_tables(struct cpu *cpu);  
350    
351    
352  #endif  /*  CPU_MIPS_H  */  #endif  /*  CPU_MIPS_H  */
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