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#define CPU_ARM_H |
#define CPU_ARM_H |
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/* |
/* |
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* Copyright (C) 2005 Anders Gavare. All rights reserved. |
* Copyright (C) 2005-2006 Anders Gavare. All rights reserved. |
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* |
* |
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* Redistribution and use in source and binary forms, with or without |
* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
* modification, are permitted provided that the following conditions are met: |
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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.h,v 1.57 2005/11/16 21:15:19 debug Exp $ |
* $Id: cpu_arm.h,v 1.65 2006/02/17 18:38:30 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ |
"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ |
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"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } |
"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } |
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#ifdef ONEKPAGE |
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#define ARM_IC_ENTRIES_SHIFT 8 |
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#else |
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#define ARM_IC_ENTRIES_SHIFT 10 |
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#endif |
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#define ARM_N_IC_ARGS 3 |
#define ARM_N_IC_ARGS 3 |
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#define ARM_INSTR_ALIGNMENT_SHIFT 2 |
#define ARM_INSTR_ALIGNMENT_SHIFT 2 |
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#define ARM_IC_ENTRIES_SHIFT 10 |
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#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) |
#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) |
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#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ |
#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ |
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& (ARM_IC_ENTRIES_PER_PAGE-1)) |
& (ARM_IC_ENTRIES_PER_PAGE-1)) |
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#define ARM_EXCEPTION_FIQ 7 |
#define ARM_EXCEPTION_FIQ 7 |
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#define ARM_N_VPH_ENTRIES 1048576 |
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#define ARM_MAX_VPH_TLB_ENTRIES 128 |
#define ARM_MAX_VPH_TLB_ENTRIES 128 |
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struct arm_vpg_tlb_entry { |
struct arm_vpg_tlb_entry { |
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unsigned char valid; |
unsigned char valid; |
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/* |
/* |
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* System Control Coprocessor registers: |
* System Control Coprocessor registers: |
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*/ |
*/ |
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uint32_t control; |
uint32_t cachetype; /* Cache Type Register */ |
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uint32_t control; /* Control Register */ |
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uint32_t auxctrl; /* Aux. Control Register */ |
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uint32_t ttb; /* Translation Table Base */ |
uint32_t ttb; /* Translation Table Base */ |
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uint32_t dacr; /* Domain Access Control */ |
uint32_t dacr; /* Domain Access Control */ |
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uint32_t fsr; /* Fault Status Register */ |
uint32_t fsr; /* Fault Status Register */ |
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uint32_t far; /* Fault Address Register */ |
uint32_t far; /* Fault Address Register */ |
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uint32_t pid; /* Process Id Register */ |
uint32_t pid; /* Process Id Register */ |
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uint32_t cpar; /* CoProcessor Access Reg. */ |
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/* i80321 Coprocessor 6: ICU (Interrupt controller) */ |
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uint32_t i80321_inten; /* enable */ |
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uint32_t i80321_isteer; |
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uint32_t i80321_isrc; /* current assertions */ |
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uint32_t tmr0; |
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uint32_t tmr1; |
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uint32_t tcr0; |
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uint32_t tcr1; |
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uint32_t trr0; |
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uint32_t trr1; |
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uint32_t tisr; |
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uint32_t wdtcr; |
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/* XScale Coprocessor 14: (Performance Monitoring Unit) */ |
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/* XSC1 access style: */ |
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uint32_t xsc1_pmnc; /* Perf. Monitor Ctrl Reg. */ |
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uint32_t xsc1_ccnt; /* Clock Counter */ |
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uint32_t xsc1_pmn0; /* Perf. Counter Reg. 0 */ |
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uint32_t xsc1_pmn1; /* Perf. Counter Reg. 1 */ |
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/* XSC2 access style: */ |
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uint32_t xsc2_pmnc; /* Perf. Monitor Ctrl Reg. */ |
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uint32_t xsc2_ccnt; /* Clock Counter */ |
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uint32_t xsc2_inten; /* Interrupt Enable */ |
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uint32_t xsc2_flag; /* Overflow Flag Register */ |
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uint32_t xsc2_evtsel; /* Event Selection Register */ |
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uint32_t xsc2_pmn0; /* Perf. Counter Reg. 0 */ |
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uint32_t xsc2_pmn1; /* Perf. Counter Reg. 1 */ |
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uint32_t xsc2_pmn2; /* Perf. Counter Reg. 2 */ |
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uint32_t xsc2_pmn3; /* Perf. Counter Reg. 3 */ |
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/* For caching the host address of the L1 translation table: */ |
/* For caching the host address of the L1 translation table: */ |
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unsigned char *translation_table; |
unsigned char *translation_table; |
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uint32_t last_ttb; |
uint32_t last_ttb; |
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/* |
/* |
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* Interrupts: |
* Interrupts: |
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*/ |
*/ |
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/* |
/* |
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* Instruction translation cache: |
* Instruction translation cache, and 32-bit virtual -> physical -> |
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* host address translation: |
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*/ |
*/ |
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DYNTRANS_ITC(arm) |
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/* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE |
VPH_TLBS(arm,ARM) |
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instruction call entries. next_ic points to the next such |
VPH32(arm,ARM,uint32_t,uint8_t) |
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call to be executed. */ |
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struct arm_tc_physpage *cur_physpage; |
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struct arm_instr_call *cur_ic_page; |
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struct arm_instr_call *next_ic; |
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void (*combination_check)(struct cpu *, |
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struct arm_instr_call *, int low_addr); |
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/* |
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* Virtual -> physical -> host address translation: |
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* |
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* host_load and host_store point to arrays of ARM_N_VPH_ENTRIES |
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* pointers (to host pages); phys_addr points to an array of |
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* ARM_N_VPH_ENTRIES uint32_t. |
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*/ |
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struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES]; |
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unsigned char *host_load[ARM_N_VPH_ENTRIES]; |
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unsigned char *host_store[ARM_N_VPH_ENTRIES]; |
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uint32_t phys_addr[ARM_N_VPH_ENTRIES]; |
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struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; |
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uint32_t phystranslation[ARM_N_VPH_ENTRIES/32]; |
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uint8_t vaddr_to_tlbindex[ARM_N_VPH_ENTRIES]; |
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/* ARM specific: */ |
/* ARM specific: */ |
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uint32_t is_userpage[ARM_N_VPH_ENTRIES/32]; |
uint32_t is_userpage[N_VPH32_ENTRIES/32]; |
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}; |
}; |
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#define ARM_CONTROL_RR 0x4000 |
#define ARM_CONTROL_RR 0x4000 |
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#define ARM_CONTROL_L4 0x8000 |
#define ARM_CONTROL_L4 0x8000 |
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/* Auxiliary Control Register bits: */ |
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#define ARM_AUXCTRL_MD 0x30 /* MiniData Cache Attribute */ |
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#define ARM_AUXCTRL_MD_SHIFT 4 |
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#define ARM_AUXCTRL_P 0x02 /* Page Table Memory Attribute */ |
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#define ARM_AUXCTRL_K 0x01 /* Write Buffer Coalescing Disable */ |
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/* Cache Type register bits: */ |
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#define ARM_CACHETYPE_CLASS 0x1e000000 |
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#define ARM_CACHETYPE_CLASS_SHIFT 25 |
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#define ARM_CACHETYPE_HARVARD 0x01000000 |
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#define ARM_CACHETYPE_HARVARD_SHIFT 24 |
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#define ARM_CACHETYPE_DSIZE 0x001c0000 |
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#define ARM_CACHETYPE_DSIZE_SHIFT 18 |
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#define ARM_CACHETYPE_DASSOC 0x00038000 |
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#define ARM_CACHETYPE_DASSOC_SHIFT 15 |
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#define ARM_CACHETYPE_DLINE 0x00003000 |
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#define ARM_CACHETYPE_DLINE_SHIFT 12 |
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#define ARM_CACHETYPE_ISIZE 0x000001c0 |
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#define ARM_CACHETYPE_ISIZE_SHIFT 6 |
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#define ARM_CACHETYPE_IASSOC 0x00000038 |
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#define ARM_CACHETYPE_IASSOC_SHIFT 3 |
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#define ARM_CACHETYPE_ILINE 0x00000003 |
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#define ARM_CACHETYPE_ILINE_SHIFT 0 |
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/* cpu_arm.c: */ |
/* cpu_arm.c: */ |
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void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
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void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
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/* cpu_arm_coproc.c: */ |
/* cpu_arm_coproc.c: */ |
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void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
int crn, int crm, int rd); |
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void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
void arm_coproc_i80321_6(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
int crn, int crm, int rd); |
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void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
void arm_coproc_xscale_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
int crn, int crm, int rd); |
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/* memory_arm.c: */ |
/* memory_arm.c: */ |