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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $ |
* $Id: cpu_arm.h,v 1.43 2005/10/07 22:10:53 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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struct cpu_family; |
struct cpu_family; |
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/* ARM CPU types: */ |
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struct arm_cpu_type_def { |
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char *name; |
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uint32_t cpu_id; |
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int flags; |
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int icache_shift; |
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int iway; |
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int dcache_shift; |
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int dway; |
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}; |
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#define ARM_SL 10 |
#define ARM_SL 10 |
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#define ARM_FP 11 |
#define ARM_FP 11 |
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#define ARM_IP 12 |
#define ARM_IP 12 |
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#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
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#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
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#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
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#define ARM_FLAG_Q 0x08000000 /* DSP saturation overflow */ |
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#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
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#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
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#define ARM_FLAG_T 0x00000020 /* Thumb mode */ |
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#define ARM_FLAG_MODE 0x0000001f |
#define ARM_FLAG_MODE 0x0000001f |
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#define ARM_MODE_USR26 0x00 |
#define ARM_MODE_USR26 0x00 |
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#define ARM_MODE_SVC32 0x13 |
#define ARM_MODE_SVC32 0x13 |
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#define ARM_MODE_ABT32 0x17 |
#define ARM_MODE_ABT32 0x17 |
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#define ARM_MODE_UND32 0x1b |
#define ARM_MODE_UND32 0x1b |
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#define ARM_MODE_SYS32 0x1f |
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#define ARM_EXCEPTION_TO_MODE { \ |
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ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \ |
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ARM_MODE_ABT32, 0, ARM_MODE_IRQ32, ARM_MODE_FIQ32 } |
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#define N_ARM_EXCEPTIONS 8 |
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#define ARM_EXCEPTION_RESET 0 |
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#define ARM_EXCEPTION_UND 1 |
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#define ARM_EXCEPTION_SWI 2 |
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#define ARM_EXCEPTION_PREF_ABT 3 |
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#define ARM_EXCEPTION_DATA_ABT 4 |
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/* 5 was address exception in 26-bit ARM */ |
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#define ARM_EXCEPTION_IRQ 6 |
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#define ARM_EXCEPTION_FIQ 7 |
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#define ARM_N_VPH_ENTRIES 1048576 |
#define ARM_N_VPH_ENTRIES 1048576 |
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#define ARM_MAX_VPH_TLB_ENTRIES 256 |
#define ARM_MAX_VPH_TLB_ENTRIES 64 |
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struct arm_vpg_tlb_entry { |
struct arm_vpg_tlb_entry { |
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int valid; |
int valid; |
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int writeflag; |
int writeflag; |
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/* |
/* |
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* Misc.: |
* Misc.: |
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*/ |
*/ |
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uint32_t flags; |
struct arm_cpu_type_def cpu_type; |
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uint32_t of_emul_addr; |
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void (*coproc[16])(struct cpu *, int opcode1, |
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int opcode2, int l_bit, int crn, int crm, |
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int rd); |
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/* |
/* |
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* General Purpose Registers (including the program counter): |
* General Purpose Registers (including the program counter): |
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*/ |
*/ |
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uint32_t r[N_ARM_REGS]; |
uint32_t r[N_ARM_REGS]; |
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uint32_t usr_r8_r14[7]; |
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uint32_t default_r8_r14[7]; /* usr and sys */ |
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uint32_t fiq_r8_r14[7]; |
uint32_t fiq_r8_r14[7]; |
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uint32_t irq_r13_r14[2]; |
uint32_t irq_r13_r14[2]; |
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uint32_t svc_r13_r14[2]; |
uint32_t svc_r13_r14[2]; |
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uint32_t abt_r13_r14[2]; |
uint32_t abt_r13_r14[2]; |
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uint32_t und_r13_r14[2]; |
uint32_t und_r13_r14[2]; |
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uint32_t tmp_pc; /* Used for load/stores */ |
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/* Flag/status registers: */ |
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uint32_t cpsr; |
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uint32_t spsr_svc; |
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uint32_t spsr_abt; |
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uint32_t spsr_und; |
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uint32_t spsr_irq; |
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uint32_t spsr_fiq; |
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/* |
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* System Control Coprocessor registers: |
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*/ |
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uint32_t control; |
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uint32_t ttb; /* Translation Table Base */ |
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uint32_t dacr; /* Domain Access Control */ |
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uint32_t fsr; /* Fault Status Register */ |
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uint32_t far; /* Fault Address Register */ |
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uint32_t pid; /* Process Id Register */ |
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/* |
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* Interrupts: |
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*/ |
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int irq_asserted; |
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/* |
/* |
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* Instruction translation cache: |
* Instruction translation cache: |
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}; |
}; |
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/* System Control Coprocessor, control bits: */ |
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#define ARM_CONTROL_MMU 0x0001 |
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#define ARM_CONTROL_ALIGN 0x0002 |
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#define ARM_CONTROL_CACHE 0x0004 |
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#define ARM_CONTROL_WBUFFER 0x0008 |
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#define ARM_CONTROL_PROG32 0x0010 |
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#define ARM_CONTROL_DATA32 0x0020 |
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#define ARM_CONTROL_BIG 0x0080 |
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#define ARM_CONTROL_S 0x0100 |
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#define ARM_CONTROL_R 0x0200 |
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#define ARM_CONTROL_F 0x0400 |
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#define ARM_CONTROL_Z 0x0800 |
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#define ARM_CONTROL_ICACHE 0x1000 |
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#define ARM_CONTROL_V 0x2000 |
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#define ARM_CONTROL_RR 0x4000 |
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#define ARM_CONTROL_L4 0x8000 |
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/* cpu_arm.c: */ |
/* cpu_arm.c: */ |
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void arm_exception(struct cpu *, int); |
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void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
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void arm_invalidate_code_translation_caches(struct cpu *cpu); |
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
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void arm_load_register_bank(struct cpu *cpu); |
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void arm_save_register_bank(struct cpu *cpu); |
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int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int arm_cpu_family_init(struct cpu_family *); |
int arm_cpu_family_init(struct cpu_family *); |
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/* cpu_arm_coproc.c: */ |
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void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
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void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
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void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit, |
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int crn, int crm, int rd); |
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/* memory_arm.c: */ |
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int arm_translate_address(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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#endif /* CPU_ARM_H */ |
#endif /* CPU_ARM_H */ |