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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.h,v 1.44 2005/10/10 18:43:37 debug Exp $ |
* $Id: cpu_arm.h,v 1.53 2005/10/27 14:01:15 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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/* Translation cache struct for each physical page: */ |
/* Translation cache struct for each physical page: */ |
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struct arm_tc_physpage { |
struct arm_tc_physpage { |
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struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1]; |
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uint32_t next_ofs; /* or 0 for end of chain */ |
uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
uint32_t physaddr; |
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int flags; |
int flags; |
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struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1]; |
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}; |
}; |
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#define ARM_N_VPH_ENTRIES 1048576 |
#define ARM_N_VPH_ENTRIES 1048576 |
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#define ARM_MAX_VPH_TLB_ENTRIES 32 |
#define ARM_MAX_VPH_TLB_ENTRIES 128 |
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struct arm_vpg_tlb_entry { |
struct arm_vpg_tlb_entry { |
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int valid; |
int valid; |
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int writeflag; |
int writeflag; |
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uint32_t far; /* Fault Address Register */ |
uint32_t far; /* Fault Address Register */ |
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uint32_t pid; /* Process Id Register */ |
uint32_t pid; /* Process Id Register */ |
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/* For caching the host address of the L1 translation table: */ |
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unsigned char *translation_table; |
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uint32_t last_ttb; |
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/* |
/* |
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* Interrupts: |
* Interrupts: |
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unsigned char *host_store[ARM_N_VPH_ENTRIES]; |
unsigned char *host_store[ARM_N_VPH_ENTRIES]; |
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uint32_t phys_addr[ARM_N_VPH_ENTRIES]; |
uint32_t phys_addr[ARM_N_VPH_ENTRIES]; |
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struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; |
struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; |
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uint32_t phystranslation[ARM_N_VPH_ENTRIES/32]; |
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int16_t vaddr_to_tlbindex[ARM_N_VPH_ENTRIES]; |
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/* ARM specific: */ |
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unsigned char is_userpage[ARM_N_VPH_ENTRIES/8]; |
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}; |
}; |
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#define ARM_CONTROL_L4 0x8000 |
#define ARM_CONTROL_L4 0x8000 |
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/* cpu_arm.c: */ |
/* cpu_arm.c: */ |
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void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
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void arm_translation_table_set_l1(struct cpu *cpu, uint32_t vaddr, |
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uint32_t paddr); |
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void arm_translation_table_set_l1_b(struct cpu *cpu, uint32_t vaddr, |
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uint32_t paddr); |
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void arm_exception(struct cpu *, int); |
void arm_exception(struct cpu *, int); |
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void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int); |
void arm_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
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void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
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void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr); |
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void arm_load_register_bank(struct cpu *cpu); |
void arm_load_register_bank(struct cpu *cpu); |
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void arm_save_register_bank(struct cpu *cpu); |
void arm_save_register_bank(struct cpu *cpu); |
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int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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/* memory_arm.c: */ |
/* memory_arm.c: */ |
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int arm_translate_address(struct cpu *cpu, uint64_t vaddr, |
int arm_translate_address(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
uint64_t *return_addr, int flags); |
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int arm_translate_address_mmu(struct cpu *cpu, uint64_t vaddr, |
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uint64_t *return_addr, int flags); |
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#endif /* CPU_ARM_H */ |
#endif /* CPU_ARM_H */ |