Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.905 2005/08/16 09:16:24 debug Exp $ 20050628 Continuing the work on the ARM translation engine. end_of_page works. Experimenting with load/store translation caches (virtual -> physical -> host). 20050629 More ARM stuff (memory access translation cache, mostly). This might break a lot of stuff elsewhere, probably some MIPS- related translation things. 20050630 Many load/stores are now automatically generated and included into cpu_arm_instr.c; 1024 functions in total (!). Fixes based on feedback from Alec Voropay: only print 8 hex digits instead of 16 in some cases when emulating 32-bit machines; similar 8 vs 16 digit fix for breakpoint addresses; 4Kc has 16 TLB entries, not 48; the MIPS config select1 register is now printed with "reg ,0". Also changing many other occurances of 16 vs 8 digit output. Adding cache associativity fields to mips_cpu_types.h; updating some other cache fields; making the output of mips_cpu_dumpinfo() look nicer. Generalizing the bintrans stuff for device accesses to also work with the new translation system. (This might also break some MIPS things.) Adding multi-load/store instructions to the ARM disassembler and the translator, and some optimizations of various kinds. 20050701 Adding a simple dev_disk (it can read/write sectors from disk images). 20050712 Adding dev_ether (a simple ethernet send/receive device). Debugger command "ninstrs" for toggling show_nr_of_instructions during runtime. Removing the framebuffer logo. 20050713 Continuing on dev_ether. Adding a dummy cpu_alpha (again). 20050714 More work on cpu_alpha. 20050715 More work on cpu_alpha. Many instructions work, enough to run a simple framebuffer fill test (similar to the ARM test). 20050716 More Alpha stuff. 20050717 Minor updates (Alpha stuff). 20050718 Minor updates (Alpha stuff). 20050719 Generalizing some Alpha instructions. 20050720 More Alpha-related updates. 20050721 Continuing on cpu_alpha. Importing rpb.h from NetBSD/alpha. 20050722 Alpha-related updates: userland stuff (Hello World using write() compiled statically for FreeBSD/Alpha runs fine), and more instructions are now implemented. 20050723 Fixing ldq_u and stq_u. Adding more instructions (conditional moves, masks, extracts, shifts). 20050724 More FreeBSD/Alpha userland stuff, and adding some more instructions (inserts). 20050725 Continuing on the Alpha stuff. (Adding dummy ldt/stt.) Adding a -A command line option to turn off alignment checks in some cases (for translated code). Trying to remove the old bintrans code which updated the pc and nr_of_executed_instructions for every instruction. 20050726 Making another attempt att removing the pc/nr of instructions code. This time it worked, huge performance increase for artificial test code, but performance loss for real-world code :-( so I'm scrapping that code for now. Tiny performance increase on Alpha (by using ret instead of jmp, to play nice with the Alpha's branch prediction) for the old MIPS bintrans backend. 20050727 Various minor fixes and cleanups. 20050728 Switching from a 2-level virtual to host/physical translation system for ARM emulation, to a 1-level translation. Trying to switch from 2-level to 1-level for the MIPS bintrans system as well (Alpha only, so far), but there is at least one problem: caches and/or how they work with device mappings. 20050730 Doing the 2-level to 1-level conversion for the i386 backend. The cache/device bug is still there for R2K/3K :( Various other minor updates (Malta etc). The mc146818 clock now updates the UIP bit in a way which works better with Linux for at least sgimips and Malta emulation. Beginning the work on refactoring the dyntrans system. 20050731 Continuing the dyntrans refactoring. Fixing a small but serious host alignment bug in memory_rw. Adding support for big-endian load/stores to the i386 bintrans backend. Another minor i386 bintrans backend update: stores from the zero register are now one (or two) loads shorter. The slt and sltu instructions were incorrectly implemented for the i386 backend; only using them for 32-bit mode for now. 20050801 Continuing the dyntrans refactoring. Cleanup of the ns16550 serial controller (removing unnecessary code). Bugfix (memory corruption bug) in dev_gt, and a patch/hack from Alec Voropay for Linux/Malta. 20050802 More cleanup/refactoring of the dyntrans subsystem: adding phys_page pointers to the lookup tables, for quick jumps between translated pages. Better fix for the ns16550 device (but still no real FIFO functionality). Converting cpu_ppc to the new dyntrans system. This means that I will have to start from scratch with implementing each instruction, and figure out how to implement dual 64/32-bit modes etc. Removing the URISC CPU family, because it was useless. 20050803 When selecting a machine type, the main type can now be omitted if the subtype name is unique. (I.e. -E can be omitted.) Fixing a dyntrans/device update bug. (Writes to offset 0 of a device could sometimes go unnoticed.) Adding an experimental "instruction combination" hack for ARM for memset-like byte fill loops. 20050804 Minor progress on cpu_alpha and related things. Finally fixing the MIPS dmult/dmultu bugs. Fixing some minor TODOs. 20050805 Generalizing the 8259 PIC. It now also works with Cobalt and evbmips emulation, in addition to the x86 hack. Finally converting the ns16550 device to use devinit. Continuing the work on the dyntrans system. Thinking about how to add breakpoints. 20050806 More dyntrans updates. Breakpoints seem to work now. 20050807 Minor updates: cpu_alpha and related things; removing dev_malta (as it isn't used any more). Dyntrans: working on general "show trace tree" support. The trace tree stuff now works with both the old MIPS code and with newer dyntrans modes. :) Continuing on Alpha-related stuff (trying to get *BSD to boot a bit further, adding more instructions, etc). 20050808 Adding a dummy IA64 cpu family, and continuing the refactoring of the dyntrans system. Removing the regression test stuff, because it was more or less useless. Adding loadlinked/storeconditional type instructions to the Alpha emulation. (Needed for Linux/alpha. Not very well tested yet.) 20050809 The function call trace tree now prints a per-function nr of arguments. (Semi-meaningless, since that data isn't read yet from the ELFs; some hardcoded symbols such as memcpy() and strlen() work fine, though.) More dyntrans refactoring; taking out more of the things that are common to all cpu families. 20050810 Working on adding support for "dual mode" for PPC dyntrans (i.e. both 64-bit and 32-bit modes). (Re)adding some simple PPC instructions. 20050811 Adding a dummy M68K cpu family. The dyntrans system isn't ready for variable-length ISAs yet, so it's completely bogus so far. Re-adding more PPC instructions. Adding a hack to src/file.c which allows OpenBSD/mac68k a.out kernels to be loaded. Beginning to add PPC loads/stores. So far they only work in 32-bit mode. 20050812 The configure file option "add_remote" now accepts symbolic host names, in addition to numeric IPv4 addresses. Re-adding more PPC instructions. 20050814 Continuing to port back more PPC instructions. Found and fixed the cache/device write-update bug for 32-bit MIPS bintrans. :-) Triggered a really weird and annoying bug in Compaq's C compiler; ccc sometimes outputs code which loads from an address _before_ checking whether the pointer was NULL or not. (I'm not sure how to handle this problem.) 20050815 Removing all of the old x86 instruction execution code; adding a new (dummy) dyntrans module for x86. Taking the first steps to extend the dyntrans system to support variable-length instructions. Slowly preparing for the next release. 20050816 Adding a dummy SPARC cpu module. Minor updates (documentation etc) for the release. ============== RELEASE 0.3.5 ==============
1 | #ifndef CPU_ARM_H |
2 | #define CPU_ARM_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | |
37 | struct cpu_family; |
38 | |
39 | #define ARM_SL 10 |
40 | #define ARM_FP 11 |
41 | #define ARM_IP 12 |
42 | #define ARM_SP 13 |
43 | #define ARM_LR 14 |
44 | #define ARM_PC 15 |
45 | #define N_ARM_REGS 16 |
46 | |
47 | #define ARM_REG_NAMES { \ |
48 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
49 | "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" } |
50 | |
51 | #define ARM_CONDITION_STRINGS { \ |
52 | "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \ |
53 | "hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" } |
54 | |
55 | /* Names of Data Processing Instructions: */ |
56 | #define ARM_DPI_NAMES { \ |
57 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ |
58 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } |
59 | |
60 | #define ARM_N_IC_ARGS 3 |
61 | #define ARM_INSTR_ALIGNMENT_SHIFT 2 |
62 | #define ARM_IC_ENTRIES_SHIFT 10 |
63 | #define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) |
64 | #define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ |
65 | & (ARM_IC_ENTRIES_PER_PAGE-1)) |
66 | #define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \ |
67 | + ARM_INSTR_ALIGNMENT_SHIFT)) |
68 | |
69 | struct arm_instr_call { |
70 | void (*f)(struct cpu *, struct arm_instr_call *); |
71 | size_t arg[ARM_N_IC_ARGS]; |
72 | }; |
73 | |
74 | /* Translation cache struct for each physical page: */ |
75 | struct arm_tc_physpage { |
76 | uint32_t next_ofs; /* or 0 for end of chain */ |
77 | uint32_t physaddr; |
78 | int flags; |
79 | struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1]; |
80 | }; |
81 | |
82 | |
83 | #define ARM_FLAG_N 0x80000000 /* Negative flag */ |
84 | #define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
85 | #define ARM_FLAG_C 0x20000000 /* Carry flag */ |
86 | #define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
87 | #define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
88 | #define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
89 | |
90 | #define ARM_FLAG_MODE 0x0000001f |
91 | #define ARM_MODE_USR26 0x00 |
92 | #define ARM_MODE_FIQ26 0x01 |
93 | #define ARM_MODE_IRQ26 0x02 |
94 | #define ARM_MODE_SVC26 0x03 |
95 | #define ARM_MODE_USR32 0x10 |
96 | #define ARM_MODE_FIQ32 0x11 |
97 | #define ARM_MODE_IRQ32 0x12 |
98 | #define ARM_MODE_SVC32 0x13 |
99 | #define ARM_MODE_ABT32 0x17 |
100 | #define ARM_MODE_UND32 0x1b |
101 | |
102 | |
103 | #define ARM_N_VPH_ENTRIES 1048576 |
104 | |
105 | #define ARM_MAX_VPH_TLB_ENTRIES 256 |
106 | struct arm_vpg_tlb_entry { |
107 | int valid; |
108 | int writeflag; |
109 | int64_t timestamp; |
110 | unsigned char *host_page; |
111 | uint32_t vaddr_page; |
112 | uint32_t paddr_page; |
113 | }; |
114 | |
115 | |
116 | struct arm_cpu { |
117 | /* |
118 | * Misc.: |
119 | */ |
120 | uint32_t flags; |
121 | |
122 | |
123 | /* |
124 | * General Purpose Registers (including the program counter): |
125 | * |
126 | * r[] always contains the current register set. The others are |
127 | * only used to swap to/from when changing modes. (An exception is |
128 | * r[0..7], which are never swapped out, they are always present.) |
129 | */ |
130 | |
131 | uint32_t r[N_ARM_REGS]; |
132 | uint32_t usr_r8_r14[7]; |
133 | uint32_t fiq_r8_r14[7]; |
134 | uint32_t irq_r13_r14[2]; |
135 | uint32_t svc_r13_r14[2]; |
136 | uint32_t abt_r13_r14[2]; |
137 | uint32_t und_r13_r14[2]; |
138 | |
139 | |
140 | /* |
141 | * Instruction translation cache: |
142 | */ |
143 | |
144 | /* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE |
145 | instruction call entries. next_ic points to the next such |
146 | call to be executed. */ |
147 | struct arm_tc_physpage *cur_physpage; |
148 | struct arm_instr_call *cur_ic_page; |
149 | struct arm_instr_call *next_ic; |
150 | |
151 | |
152 | /* |
153 | * Virtual -> physical -> host address translation: |
154 | * |
155 | * host_load and host_store point to arrays of ARM_N_VPH_ENTRIES |
156 | * pointers (to host pages); phys_addr points to an array of |
157 | * ARM_N_VPH_ENTRIES uint32_t. |
158 | */ |
159 | |
160 | struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES]; |
161 | unsigned char *host_load[ARM_N_VPH_ENTRIES]; |
162 | unsigned char *host_store[ARM_N_VPH_ENTRIES]; |
163 | uint32_t phys_addr[ARM_N_VPH_ENTRIES]; |
164 | struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; |
165 | }; |
166 | |
167 | |
168 | /* cpu_arm.c: */ |
169 | void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
170 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
171 | void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
172 | void arm_invalidate_code_translation_caches(struct cpu *cpu); |
173 | int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
174 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
175 | int arm_cpu_family_init(struct cpu_family *); |
176 | |
177 | |
178 | #endif /* CPU_ARM_H */ |
ViewVC Help | |
Powered by ViewVC 1.1.26 |