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* SUCH DAMAGE. |
* SUCH DAMAGE. |
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* |
* |
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* |
* |
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* $Id: cpu_arm.h,v 1.1 2005/06/03 07:39:28 debug Exp $ |
* $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $ |
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*/ |
*/ |
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#include "misc.h" |
#include "misc.h" |
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struct cpu_family; |
struct cpu_family; |
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#define ARM_SL 10 |
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#define ARM_FP 11 |
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#define ARM_IP 12 |
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#define ARM_SP 13 |
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#define ARM_LR 14 |
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#define ARM_PC 15 |
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#define N_ARM_REGS 16 |
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#define ARM_REG_NAMES { \ |
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
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"r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" } |
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#define ARM_CONDITION_STRINGS { \ |
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"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", \ |
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"hi", "ls", "ge", "lt", "gt", "le", "" /*Always*/ , "(INVALID)" } |
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/* Names of Data Processing Instructions: */ |
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#define ARM_DPI_NAMES { \ |
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"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", \ |
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"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn" } |
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#define ARM_N_IC_ARGS 3 |
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#define ARM_INSTR_ALIGNMENT_SHIFT 2 |
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#define ARM_IC_ENTRIES_SHIFT 10 |
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#define ARM_IC_ENTRIES_PER_PAGE (1 << ARM_IC_ENTRIES_SHIFT) |
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#define ARM_PC_TO_IC_ENTRY(a) (((a)>>ARM_INSTR_ALIGNMENT_SHIFT) \ |
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& (ARM_IC_ENTRIES_PER_PAGE-1)) |
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#define ARM_ADDR_TO_PAGENR(a) ((a) >> (ARM_IC_ENTRIES_SHIFT \ |
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+ ARM_INSTR_ALIGNMENT_SHIFT)) |
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struct arm_instr_call { |
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void (*f)(struct cpu *, struct arm_instr_call *); |
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size_t arg[ARM_N_IC_ARGS]; |
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}; |
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/* Translation cache struct for each physical page: */ |
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struct arm_tc_physpage { |
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uint32_t next_ofs; /* or 0 for end of chain */ |
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uint32_t physaddr; |
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int flags; |
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struct arm_instr_call ics[ARM_IC_ENTRIES_PER_PAGE + 1]; |
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}; |
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#define ARM_FLAG_N 0x80000000 /* Negative flag */ |
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#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
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#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
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#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
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#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
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#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
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#define ARM_FLAG_MODE 0x0000001f |
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#define ARM_MODE_USR26 0x00 |
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#define ARM_MODE_FIQ26 0x01 |
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#define ARM_MODE_IRQ26 0x02 |
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#define ARM_MODE_SVC26 0x03 |
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#define ARM_MODE_USR32 0x10 |
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#define ARM_MODE_FIQ32 0x11 |
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#define ARM_MODE_IRQ32 0x12 |
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#define ARM_MODE_SVC32 0x13 |
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#define ARM_MODE_ABT32 0x17 |
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#define ARM_MODE_UND32 0x1b |
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#define ARM_N_VPH_ENTRIES 1048576 |
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#define ARM_MAX_VPH_TLB_ENTRIES 256 |
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struct arm_vpg_tlb_entry { |
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int valid; |
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int writeflag; |
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int64_t timestamp; |
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unsigned char *host_page; |
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uint32_t vaddr_page; |
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uint32_t paddr_page; |
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}; |
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struct arm_cpu { |
struct arm_cpu { |
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int dummy; |
/* |
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* Misc.: |
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*/ |
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uint32_t flags; |
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/* |
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* General Purpose Registers (including the program counter): |
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* |
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* r[] always contains the current register set. The others are |
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* only used to swap to/from when changing modes. (An exception is |
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* r[0..7], which are never swapped out, they are always present.) |
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*/ |
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uint32_t r[N_ARM_REGS]; |
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uint32_t usr_r8_r14[7]; |
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uint32_t fiq_r8_r14[7]; |
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uint32_t irq_r13_r14[2]; |
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uint32_t svc_r13_r14[2]; |
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uint32_t abt_r13_r14[2]; |
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uint32_t und_r13_r14[2]; |
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/* |
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* Instruction translation cache: |
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*/ |
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/* cur_ic_page is a pointer to an array of ARM_IC_ENTRIES_PER_PAGE |
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instruction call entries. next_ic points to the next such |
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call to be executed. */ |
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struct arm_tc_physpage *cur_physpage; |
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struct arm_instr_call *cur_ic_page; |
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struct arm_instr_call *next_ic; |
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/* |
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* Virtual -> physical -> host address translation: |
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* |
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* host_load and host_store point to arrays of ARM_N_VPH_ENTRIES |
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* pointers (to host pages); phys_addr points to an array of |
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* ARM_N_VPH_ENTRIES uint32_t. |
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*/ |
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struct arm_vpg_tlb_entry vph_tlb_entry[ARM_MAX_VPH_TLB_ENTRIES]; |
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unsigned char *host_load[ARM_N_VPH_ENTRIES]; |
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unsigned char *host_store[ARM_N_VPH_ENTRIES]; |
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uint32_t phys_addr[ARM_N_VPH_ENTRIES]; |
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struct arm_tc_physpage *phys_page[ARM_N_VPH_ENTRIES]; |
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}; |
}; |
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/* cpu_arm.c: */ |
/* cpu_arm.c: */ |
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void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
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unsigned char *host_page, int writeflag, uint64_t paddr_page); |
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void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr); |
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void arm_invalidate_code_translation_caches(struct cpu *cpu); |
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int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
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unsigned char *data, size_t len, int writeflag, int cache_flags); |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
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int arm_cpu_family_init(struct cpu_family *); |
int arm_cpu_family_init(struct cpu_family *); |
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