--- trunk/src/include/cpu_arm.h	2007/10/08 16:18:38	12
+++ trunk/src/include/cpu_arm.h	2007/10/08 16:18:51	14
@@ -28,7 +28,7 @@
  *  SUCH DAMAGE.
  *
  *
- *  $Id: cpu_arm.h,v 1.26 2005/08/14 23:44:23 debug Exp $
+ *  $Id: cpu_arm.h,v 1.43 2005/10/07 22:10:53 debug Exp $
  */
 
 #include "misc.h"
@@ -36,6 +36,18 @@
 
 struct cpu_family;
 
+/*  ARM CPU types:  */
+struct arm_cpu_type_def {
+	char		*name;
+	uint32_t	cpu_id;
+	int		flags;
+	int		icache_shift;
+	int		iway;
+	int		dcache_shift;
+	int		dway;
+};
+
+
 #define	ARM_SL			10
 #define	ARM_FP			11
 #define	ARM_IP			12
@@ -84,8 +96,10 @@
 #define	ARM_FLAG_Z	0x40000000	/*  Zero flag  */
 #define	ARM_FLAG_C	0x20000000	/*  Carry flag  */
 #define	ARM_FLAG_V	0x10000000	/*  Overflow flag  */
+#define	ARM_FLAG_Q	0x08000000	/*  DSP saturation overflow  */
 #define	ARM_FLAG_I	0x00000080	/*  Interrupt disable  */
 #define	ARM_FLAG_F	0x00000040	/*  Fast Interrupt disable  */
+#define	ARM_FLAG_T	0x00000020	/*  Thumb mode  */
 
 #define	ARM_FLAG_MODE	0x0000001f
 #define	ARM_MODE_USR26	      0x00
@@ -98,11 +112,27 @@
 #define	ARM_MODE_SVC32	      0x13
 #define	ARM_MODE_ABT32	      0x17
 #define	ARM_MODE_UND32	      0x1b
+#define	ARM_MODE_SYS32	      0x1f
+
+#define ARM_EXCEPTION_TO_MODE	{	\
+	ARM_MODE_SVC32, ARM_MODE_UND32, ARM_MODE_SVC32, ARM_MODE_ABT32, \
+	ARM_MODE_ABT32, 0,              ARM_MODE_IRQ32, ARM_MODE_FIQ32 	}
+
+#define	N_ARM_EXCEPTIONS	8
+
+#define	ARM_EXCEPTION_RESET	0
+#define	ARM_EXCEPTION_UND	1
+#define	ARM_EXCEPTION_SWI	2
+#define	ARM_EXCEPTION_PREF_ABT	3
+#define	ARM_EXCEPTION_DATA_ABT	4
+/*  5 was address exception in 26-bit ARM  */
+#define	ARM_EXCEPTION_IRQ	6
+#define	ARM_EXCEPTION_FIQ	7
 
 
 #define	ARM_N_VPH_ENTRIES	1048576
 
-#define	ARM_MAX_VPH_TLB_ENTRIES		256
+#define	ARM_MAX_VPH_TLB_ENTRIES		64
 struct arm_vpg_tlb_entry {
 	int		valid;
 	int		writeflag;
@@ -117,8 +147,12 @@
 	/*
 	 *  Misc.:
 	 */
-	uint32_t		flags;
+	struct arm_cpu_type_def	cpu_type;
+	uint32_t		of_emul_addr;
 
+	void			(*coproc[16])(struct cpu *, int opcode1,
+				    int opcode2, int l_bit, int crn, int crm,
+				    int rd);
 
 	/*
 	 *  General Purpose Registers (including the program counter):
@@ -129,13 +163,41 @@
 	 */
 
 	uint32_t		r[N_ARM_REGS];
-	uint32_t		usr_r8_r14[7];
+
+	uint32_t		default_r8_r14[7];	/*  usr and sys  */
 	uint32_t		fiq_r8_r14[7];
 	uint32_t		irq_r13_r14[2];
 	uint32_t		svc_r13_r14[2];
 	uint32_t		abt_r13_r14[2];
 	uint32_t		und_r13_r14[2];
 
+	uint32_t		tmp_pc;		/*  Used for load/stores  */
+
+	/*  Flag/status registers:  */
+	uint32_t		cpsr;
+	uint32_t		spsr_svc;
+	uint32_t		spsr_abt;
+	uint32_t		spsr_und;
+	uint32_t		spsr_irq;
+	uint32_t		spsr_fiq;
+
+
+	/*
+	 *  System Control Coprocessor registers:
+	 */
+	uint32_t		control;
+	uint32_t		ttb;		/*  Translation Table Base  */
+	uint32_t		dacr;		/*  Domain Access Control  */
+	uint32_t		fsr;		/*  Fault Status Register  */
+	uint32_t		far;		/*  Fault Address Register  */
+	uint32_t		pid;		/*  Process Id Register  */
+
+
+	/*
+	 *  Interrupts:
+	 */
+	int			irq_asserted;
+
 
 	/*
 	 *  Instruction translation cache:
@@ -165,14 +227,46 @@
 };
 
 
+/*  System Control Coprocessor, control bits:  */
+#define	ARM_CONTROL_MMU		0x0001
+#define	ARM_CONTROL_ALIGN	0x0002
+#define	ARM_CONTROL_CACHE	0x0004
+#define	ARM_CONTROL_WBUFFER	0x0008
+#define	ARM_CONTROL_PROG32	0x0010
+#define	ARM_CONTROL_DATA32	0x0020
+#define	ARM_CONTROL_BIG		0x0080
+#define	ARM_CONTROL_S		0x0100
+#define	ARM_CONTROL_R		0x0200
+#define	ARM_CONTROL_F		0x0400
+#define	ARM_CONTROL_Z		0x0800
+#define	ARM_CONTROL_ICACHE	0x1000
+#define	ARM_CONTROL_V		0x2000
+#define	ARM_CONTROL_RR		0x4000
+#define	ARM_CONTROL_L4		0x8000
+
 /*  cpu_arm.c:  */
+void arm_exception(struct cpu *, int);
 void arm_update_translation_table(struct cpu *cpu, uint64_t vaddr_page,
 	unsigned char *host_page, int writeflag, uint64_t paddr_page);
-void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t paddr);
-void arm_invalidate_code_translation_caches(struct cpu *cpu);
+void arm_invalidate_translation_caches_paddr(struct cpu *cpu, uint64_t, int);
+void arm_invalidate_code_translation(struct cpu *cpu, uint64_t, int);
+void arm_setup_initial_translation_table(struct cpu *cpu, uint32_t ttb_addr);
+void arm_load_register_bank(struct cpu *cpu);
+void arm_save_register_bank(struct cpu *cpu);
 int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr,
 	unsigned char *data, size_t len, int writeflag, int cache_flags);
 int arm_cpu_family_init(struct cpu_family *);
 
+/*  cpu_arm_coproc.c:  */
+void arm_coproc_15(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd);
+void arm_coproc_i80321(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd);
+void arm_coproc_i80321_14(struct cpu *cpu, int opcode1, int opcode2, int l_bit,
+	int crn, int crm, int rd);
+
+/*  memory_arm.c:  */
+int arm_translate_address(struct cpu *cpu, uint64_t vaddr,
+	uint64_t *return_addr, int flags);
 
 #endif	/*  CPU_ARM_H  */