1 |
#ifndef CPU_ARM_H |
2 |
#define CPU_ARM_H |
3 |
|
4 |
/* |
5 |
* Copyright (C) 2005 Anders Gavare. All rights reserved. |
6 |
* |
7 |
* Redistribution and use in source and binary forms, with or without |
8 |
* modification, are permitted provided that the following conditions are met: |
9 |
* |
10 |
* 1. Redistributions of source code must retain the above copyright |
11 |
* notice, this list of conditions and the following disclaimer. |
12 |
* 2. Redistributions in binary form must reproduce the above copyright |
13 |
* notice, this list of conditions and the following disclaimer in the |
14 |
* documentation and/or other materials provided with the distribution. |
15 |
* 3. The name of the author may not be used to endorse or promote products |
16 |
* derived from this software without specific prior written permission. |
17 |
* |
18 |
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 |
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 |
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 |
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 |
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 |
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 |
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 |
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 |
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 |
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 |
* SUCH DAMAGE. |
29 |
* |
30 |
* |
31 |
* $Id: cpu_arm.h,v 1.10 2005/06/26 22:23:43 debug Exp $ |
32 |
*/ |
33 |
|
34 |
#include "misc.h" |
35 |
|
36 |
|
37 |
struct cpu_family; |
38 |
|
39 |
#define ARM_SL 10 |
40 |
#define ARM_FP 11 |
41 |
#define ARM_IP 12 |
42 |
#define ARM_SP 13 |
43 |
#define ARM_LR 14 |
44 |
#define ARM_PC 15 |
45 |
#define N_ARM_REGS 16 |
46 |
|
47 |
/* |
48 |
* Translated instruction calls: |
49 |
* |
50 |
* The translation cache begins with N_BASE_TABLE_ENTRIES uint32_t offsets |
51 |
* to arm_tc_physpage structs. |
52 |
*/ |
53 |
#define N_IC_ARGS 3 |
54 |
#define IC_ENTRIES_SHIFT 10 |
55 |
#define IC_ENTRIES_PER_PAGE (1 << IC_ENTRIES_SHIFT) |
56 |
#define PC_TO_IC_ENTRY(a) (((a) >> 2) & (IC_ENTRIES_PER_PAGE-1)) |
57 |
#define ADDR_TO_PAGENR(a) ((a) >> (IC_ENTRIES_SHIFT+2)) |
58 |
#define N_BASE_TABLE_ENTRIES 32768 |
59 |
#define PAGENR_TO_TABLE_INDEX(a) ((a) & (N_BASE_TABLE_ENTRIES-1)) |
60 |
#define ARM_TRANSLATION_CACHE_SIZE (1048576 * 16) |
61 |
#define ARM_TRANSLATION_CACHE_MARGIN 65536 |
62 |
|
63 |
struct arm_instr_call { |
64 |
void (*f)(struct cpu *, struct arm_instr_call *); |
65 |
size_t arg[N_IC_ARGS]; |
66 |
}; |
67 |
|
68 |
struct arm_tc_physpage { |
69 |
uint32_t next_ofs; /* or 0 for end of chain */ |
70 |
uint32_t physaddr; |
71 |
int flags; |
72 |
struct arm_instr_call ics[IC_ENTRIES_PER_PAGE + 1]; |
73 |
}; |
74 |
|
75 |
#define ARM_COMBINATIONS 1 |
76 |
|
77 |
#define ARM_FLAG_N 0x80000000 /* Negative flag */ |
78 |
#define ARM_FLAG_Z 0x40000000 /* Zero flag */ |
79 |
#define ARM_FLAG_C 0x20000000 /* Carry flag */ |
80 |
#define ARM_FLAG_V 0x10000000 /* Overflow flag */ |
81 |
#define ARM_FLAG_I 0x00000080 /* Interrupt disable */ |
82 |
#define ARM_FLAG_F 0x00000040 /* Fast Interrupt disable */ |
83 |
|
84 |
#define ARM_FLAG_MODE 0x0000001f |
85 |
#define ARM_MODE_USR26 0x00 |
86 |
#define ARM_MODE_FIQ26 0x01 |
87 |
#define ARM_MODE_IRQ26 0x02 |
88 |
#define ARM_MODE_SVC26 0x03 |
89 |
#define ARM_MODE_USR32 0x10 |
90 |
#define ARM_MODE_FIQ32 0x11 |
91 |
#define ARM_MODE_IRQ32 0x12 |
92 |
#define ARM_MODE_SVC32 0x13 |
93 |
#define ARM_MODE_ABT32 0x17 |
94 |
#define ARM_MODE_UND32 0x1b |
95 |
|
96 |
struct arm_cpu { |
97 |
uint32_t flags; |
98 |
|
99 |
/* |
100 |
* General Purpose Registers (including the program counter): |
101 |
* |
102 |
* r[] always contains the current register set. The others are |
103 |
* only used to swap to/from when changing modes. (An exception is |
104 |
* r[0..7], which are never swapped out, they are always present.) |
105 |
*/ |
106 |
uint32_t r[N_ARM_REGS]; |
107 |
uint32_t usr_r8_r14[7]; |
108 |
uint32_t fiq_r8_r14[7]; |
109 |
uint32_t irq_r13_r14[2]; |
110 |
uint32_t svc_r13_r14[2]; |
111 |
uint32_t abt_r13_r14[2]; |
112 |
uint32_t und_r13_r14[2]; |
113 |
|
114 |
/* |
115 |
* Instruction translation cache: |
116 |
*/ |
117 |
unsigned char *translation_cache; |
118 |
size_t translation_cache_cur_ofs; |
119 |
|
120 |
/* cur_ic_page is a pointer to an array of IC_ENTRIES_PER_PAGE |
121 |
instruction call entries. next_ic points to the next such |
122 |
call to be executed. */ |
123 |
struct arm_tc_physpage *cur_physpage; |
124 |
struct arm_instr_call *cur_ic_page; |
125 |
struct arm_instr_call *next_ic; |
126 |
|
127 |
int running_translated; |
128 |
int32_t n_translated_instrs; |
129 |
}; |
130 |
|
131 |
|
132 |
/* cpu_arm.c: */ |
133 |
int arm_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
134 |
unsigned char *data, size_t len, int writeflag, int cache_flags); |
135 |
int arm_cpu_family_init(struct cpu_family *); |
136 |
|
137 |
|
138 |
#endif /* CPU_ARM_H */ |