Parent Directory | Revision Log
++ trunk/HISTORY (local) $Id: HISTORY,v 1.1613 2007/06/15 20:11:26 debug Exp $ 20070501 Continuing a little on m88k disassembly (control registers, more instructions). Adding a dummy mvme88k machine mode. 20070502 Re-adding MIPS load/store alignment exceptions. 20070503 Implementing more of the M88K disassembly code. 20070504 Adding disassembly of some more M88K load/store instructions. Implementing some relatively simple M88K instructions (br.n, xor[.u] imm, and[.u] imm). 20070505 Implementing M88K three-register and, or, xor, and jmp[.n], bsr[.n] including function call trace stuff. Applying a patch from Bruce M. Simpson which implements the SYSCON_BOARD_CPU_CLOCK_FREQ_ID object of the syscon call in the yamon PROM emulation. 20070506 Implementing M88K bb0[.n] and bb1[.n], and skeletons for ldcr and stcr (although no control regs are implemented yet). 20070509 Found and fixed the bug which caused Linux for QEMU_MIPS to stop working in 0.4.5.1: It was a faulty change to the MIPS 'sc' and 'scd' instructions I made while going through gcc -W warnings on 20070428. 20070510 Updating the Linux/QEMU_MIPS section in guestoses.html to use mips-test-0.2.tar.gz instead of 0.1. A big thank you to Miod Vallat for sending me M88K manuals. Implementing more M88K instructions (addu, subu, div[u], mulu, ext[u], clr, set, cmp). 20070511 Fixing bugs in the M88K "and" and "and.u" instructions (found by comparing against the manual). Implementing more M88K instructions (mask[.u], mak, bcnd (auto- generated)) and some more control register details. Cleanup: Removing the experimental AVR emulation mode and corresponding devices; AVR emulation wasn't really meaningful. Implementing autogeneration of most M88K loads/stores. The rectangle drawing demo (with -O0) for M88K runs :-) Beginning on M88K exception handling. More M88K instructions: tb0, tb1, rte, sub, jsr[.n]. Adding some skeleton MVME PROM ("BUG") emulation. 20070512 Fixing a bug in the M88K cmp instruction. Adding the M88K lda (scaled register) instruction. Fixing bugs in 64-bit (32-bit pairs) M88K loads/stores. Removing the unused tick_hz stuff from the machine struct. Implementing the M88K xmem instruction. OpenBSD/mvme88k gets far enough to display the Copyright banner :-) Implementing subu.co (guess), addu.co, addu.ci, ff0, and ff1. Adding a dev_mvme187, for MVME187-specific devices/registers. OpenBSD/mvme88k prints more boot messages. :) 20070515 Continuing on MVME187 emulation (adding more devices, beginning on the CMMUs, etc). Adding the M88K and.c, xor.c, and or.c instructions, and making sure that mul, div, etc cause exceptions if executed when SFD1 is disabled. 20070517 Continuing on M88K and MVME187 emulation in general; moving the CMMU registers to the CPU struct, separating dev_pcc2 from dev_mvme187, and beginning on memory_m88k.c (BATC and PATC). Fixing a bug in 64-bit (32-bit pairs) M88K fast stores. Implementing the clock part of dev_mk48txx. Implementing the M88K fstcr and xcr instructions. Implementing m88k_cpu_tlbdump(). Beginning on the implementation of a separate address space for M88K .usr loads/stores. 20070520 Removing the non-working (skeleton) Sandpoint, SonyNEWS, SHARK Dnard, and Zaurus machine modes. Experimenting with dyntrans to_be_translated read-ahead. It seems to give a very small performance increase for MIPS emulation, but a large performance degradation for SuperH. Hm. 20070522 Disabling correct SuperH ITLB emulation; it does not seem to be necessary in order to let SH4 guest OSes run, and it slows down userspace code. Implementing "samepage" branches for SuperH emulation, and some other minor speed hacks. 20070525 Continuing on M88K memory-related stuff: exceptions, memory transaction register contents, etc. Implementing the M88K subu.ci instruction. Removing the non-working (skeleton) Iyonix machine mode. OpenBSD/mvme88k reaches userland :-), starts executing /sbin/init's instructions, and issues a few syscalls, before crashing. 20070526 Fixing bugs in dev_mk48txx, so that OpenBSD/mvme88k detects the correct time-of-day. Implementing a generic IRQ controller for the test machines (dev_irqc), similar to a proposed patch from Petr Stepan. Experimenting some more with translation read-ahead. Adding an "expect" script for automated OpenBSD/landisk install regression/performance tests. 20070527 Adding a dummy mmEye (SH3) machine mode skeleton. FINALLY found the strange M88K bug I have been hunting: I had not emulated the SNIP value for exceptions occurring in branch delay slots correctly. Implementing correct exceptions for 64-bit M88K loads/stores. Address to symbol lookups are now disabled when M88K is running in usermode (because usermode addresses don't have anything to do with supervisor addresses). 20070531 Removing the mmEye machine mode skeleton. 20070604 Some minor code cleanup. 20070605 Moving src/useremul.c into a subdir (src/useremul/), and cleaning up some more legacy constructs. Adding -Wstrict-aliasing and -fstrict-aliasing detection to the configure script. 20070606 Adding a check for broken GCC on Solaris to the configure script. (GCC 3.4.3 on Solaris cannot handle static variables which are initialized to 0 or NULL. :-/) Removing the old (non-working) ARC emulation modes: NEC RD94, R94, R96, and R98, and the last traces of Olivetti M700 and Deskstation Tyne. Removing the non-working skeleton WDSC device (dev_wdsc). 20070607 Thinking about how to use the host's cc + ld at runtime to generate native code. (See experiments/native_cc_ld_test.i for an example.) 20070608 Adding a program counter sampling timer, which could be useful for native code generation experiments. The KN02_CSR_NRMMOD bit in the DECstation 5000/200 (KN02) CSR should always be set, to allow a 5000/200 PROM to boot. 20070609 Moving out breakpoint details from the machine struct into a helper struct, and removing the limit on max nr of breakpoints. 20070610 Moving out tick functions into a helper struct as well (which also gets rid of the max limit). 20070612 FINALLY figured out why Debian/DECstation stopped working when translation read-ahead was enabled: in src/memory_rw.c, the call to invalidate_code_translation was made also if the memory access was an instruction load (if the page was mapped as writable); it shouldn't be called in that case. 20070613 Implementing some more MIPS32/64 revision 2 instructions: di, ei, ext, dext, dextm, dextu, and ins. 20070614 Implementing an instruction combination for the NetBSD/arm idle loop (making the host not use any cpu if NetBSD/arm inside the emulator is not using any cpu). Increasing the nr of ARM VPH entries from 128 to 384. 20070615 Removing the ENABLE_arch stuff from the configure script, so that all included architectures are included in both release and development builds. Moving memory related helper functions from misc.c to memory.c. Adding preliminary instructions for netbooting NetBSD/pmppc to guestoses.html; it doesn't work yet, there are weird timeouts. Beginning a total rewrite of the userland emulation modes (removing all emulation modes, beginning from scratch with NetBSD/MIPS and FreeBSD/Alpha only). 20070616 After fixing a bug in the DEC21143 NIC (the TDSTAT_OWN bit was only cleared for the last segment when transmitting, not all segments), NetBSD/pmppc boots with root-on-nfs without the timeouts. Updating guestoses.html. Removing the skeleton PSP (Playstation Portable) mode. Moving X11-related stuff in the machine struct into a helper struct. Cleanup of out-of-memory checks, to use a new CHECK_ALLOCATION macro (which prints a meaningful error message). Adding a COMMENT to each machine and device (for automagic .index comment generation). Doing regression testing for the next release. ============== RELEASE 0.4.6 ==============
1 | #ifndef CPU_ALPHA_H |
2 | #define CPU_ALPHA_H |
3 | |
4 | /* |
5 | * Copyright (C) 2005-2007 Anders Gavare. All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions are met: |
9 | * |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * 3. The name of the author may not be used to endorse or promote products |
16 | * derived from this software without specific prior written permission. |
17 | * |
18 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
19 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
24 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
25 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
26 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
27 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
28 | * SUCH DAMAGE. |
29 | * |
30 | * |
31 | * $Id: cpu_alpha.h,v 1.48 2007/06/07 15:36:24 debug Exp $ |
32 | */ |
33 | |
34 | #include "misc.h" |
35 | |
36 | #include "alpha_cpu.h" |
37 | |
38 | struct timer; |
39 | |
40 | |
41 | /* ALPHA CPU types: */ |
42 | struct alpha_cpu_type_def { |
43 | char *name; |
44 | uint64_t pcs_type; /* See alpha_rpb.h */ |
45 | int features; |
46 | int implver; |
47 | int icache_shift; |
48 | int ilinesize; |
49 | int iway; |
50 | int dcache_shift; |
51 | int dlinesize; |
52 | int dway; |
53 | int l2cache_shift; |
54 | int l2linesize; |
55 | int l2way; |
56 | }; |
57 | |
58 | /* TODO: More features */ |
59 | #define ALPHA_FEATURE_BWX 1 |
60 | |
61 | #define ALPHA_CPU_TYPE_DEFS { \ |
62 | { "21064", 0x000000002ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
63 | { "21066", 0x200000004ULL, 0, 0, 16,5,2, 16,5,2, 0,0,0 }, \ |
64 | { "21164", 0x000000005ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \ |
65 | { "21164A-2", 0x000000007ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \ |
66 | { "21164PC", 0x000000009ULL, 0, 1, 16,5,2, 16,5,2, 0,0,0 }, \ |
67 | { "21264", 0x00000000dULL, 0, 2, 16,5,2, 16,5,2, 0,0,0 }, \ |
68 | { "21364", 0x000000000ULL, 0, 3, 16,5,2, 16,5,2, 0,0,0 }, \ |
69 | { NULL, 0x000000000ULL, 0, 0, 0,0,0, 0,0,0, 0,0,0 } } |
70 | |
71 | |
72 | struct cpu_family; |
73 | |
74 | /* ALPHA_KENTRY_INT .. ALPHA_KENTRY_SYS */ |
75 | #define N_ALPHA_KENTRY 6 |
76 | |
77 | #define ALPHA_V0 0 |
78 | #define ALPHA_A0 16 |
79 | #define ALPHA_A1 17 |
80 | #define ALPHA_A2 18 |
81 | #define ALPHA_A3 19 |
82 | #define ALPHA_A4 20 |
83 | #define ALPHA_A5 21 |
84 | #define ALPHA_RA 26 |
85 | #define ALPHA_T12 27 |
86 | #define ALPHA_SP 30 |
87 | #define ALPHA_ZERO 31 |
88 | #define N_ALPHA_REGS 32 |
89 | |
90 | #define ALPHA_REG_NAMES { \ |
91 | "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", \ |
92 | "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", \ |
93 | "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", \ |
94 | "t10", "t11", "ra", "t12", "at", "gp", "sp", "zero" } |
95 | |
96 | |
97 | /* Dyntrans definitions: */ |
98 | |
99 | #define ALPHA_N_IC_ARGS 3 |
100 | #define ALPHA_INSTR_ALIGNMENT_SHIFT 2 |
101 | #define ALPHA_IC_ENTRIES_SHIFT 11 |
102 | #define ALPHA_IC_ENTRIES_PER_PAGE (1 << ALPHA_IC_ENTRIES_SHIFT) |
103 | #define ALPHA_PC_TO_IC_ENTRY(a) (((a)>>ALPHA_INSTR_ALIGNMENT_SHIFT) \ |
104 | & (ALPHA_IC_ENTRIES_PER_PAGE-1)) |
105 | #define ALPHA_ADDR_TO_PAGENR(a) ((a) >> (ALPHA_IC_ENTRIES_SHIFT \ |
106 | + ALPHA_INSTR_ALIGNMENT_SHIFT)) |
107 | |
108 | #define ALPHA_MAX_VPH_TLB_ENTRIES 128 |
109 | |
110 | #define ALPHA_L2N 17 |
111 | #define ALPHA_L3N 17 |
112 | |
113 | DYNTRANS_MISC_DECLARATIONS(alpha,ALPHA,uint64_t) |
114 | DYNTRANS_MISC64_DECLARATIONS(alpha,ALPHA,uint8_t) |
115 | |
116 | |
117 | #define ALPHA_PAGESHIFT 13 |
118 | |
119 | |
120 | struct alpha_cpu { |
121 | struct alpha_cpu_type_def cpu_type; |
122 | |
123 | |
124 | /* |
125 | * General Purpose Registers: |
126 | */ |
127 | |
128 | uint64_t r[N_ALPHA_REGS]; /* Integer */ |
129 | uint64_t f[N_ALPHA_REGS]; /* Floating Point */ |
130 | |
131 | uint64_t fpcr; /* FP Control Reg. */ |
132 | |
133 | /* Misc.: */ |
134 | uint64_t pcc; /* Cycle Counter */ |
135 | uint64_t ipl; |
136 | uint64_t load_linked_addr; |
137 | int ll_flag; |
138 | |
139 | int irq_asserted; |
140 | |
141 | /* OSF1 PALcode specific: */ |
142 | uint64_t vptptr; /* Virtual Page Table Ptr */ |
143 | uint64_t sysvalue; |
144 | uint64_t kgp; /* Kernel GP */ |
145 | uint64_t kentry[N_ALPHA_KENTRY]; |
146 | uint64_t ctx; /* Ptr to current PCB (?) */ |
147 | struct alpha_pcb pcb; /* Process Control Block */ |
148 | |
149 | |
150 | /* |
151 | * Instruction translation cache and Virtual->Physical->Host |
152 | * address translation: |
153 | */ |
154 | DYNTRANS_ITC(alpha) |
155 | VPH_TLBS(alpha,ALPHA) |
156 | VPH64(alpha,ALPHA) |
157 | }; |
158 | |
159 | |
160 | /* cpu_alpha.c: */ |
161 | void alpha_update_translation_table(struct cpu *cpu, uint64_t vaddr_page, |
162 | unsigned char *host_page, int writeflag, uint64_t paddr_page); |
163 | void alpha_invalidate_translation_caches(struct cpu *cpu, uint64_t, int); |
164 | void alpha_invalidate_code_translation(struct cpu *cpu, uint64_t, int); |
165 | void alpha_init_64bit_dummy_tables(struct cpu *cpu); |
166 | void alpha_timer_sample_tick(struct timer *, void *); |
167 | int alpha_run_instr(struct cpu *cpu); |
168 | int alpha_memory_rw(struct cpu *cpu, struct memory *mem, uint64_t vaddr, |
169 | unsigned char *data, size_t len, int writeflag, int cache_flags); |
170 | int alpha_userland_memory_rw(struct cpu *cpu, struct memory *mem, |
171 | uint64_t vaddr, unsigned char *data, size_t len, int writeflag, |
172 | int cache_flags); |
173 | int alpha_cpu_family_init(struct cpu_family *); |
174 | |
175 | /* cpu_alpha_palcode.c: */ |
176 | void alpha_palcode_name(uint32_t palcode, char *buf, size_t buflen); |
177 | void alpha_palcode(struct cpu *cpu, uint32_t palcode); |
178 | |
179 | /* memory_alpha.c: */ |
180 | int alpha_translate_v2p(struct cpu *cpu, uint64_t vaddr, |
181 | uint64_t *return_addr, int flags); |
182 | |
183 | |
184 | #endif /* CPU_ALPHA_H */ |
ViewVC Help | |
Powered by ViewVC 1.1.26 |